upd78f9211grt2-jjg-a ETC-unknow, upd78f9211grt2-jjg-a Datasheet - Page 342

• Manufacturer Part Number: upd78f9211grt2-jjg-a
• Description: 8-bit Single-chip Microcontrollers
• Manufacturer: ETC-unknow

342
Standby
function
Reset
function
Power-
on-clear
circuit
Low-
voltage
detector
Function
OSTS:
Oscillation
stabilization
time select
register
HALT mode
setting and
operating
statuses
STOP mode
setting and
operating
statuses
Timing of reset
by overflow of
watchdog timer
RESF: Reset
control flag
register
Functions of
power-on-clear
circuit
Cautions for
power-on-clear
circuit
LVIM: Low-
voltage detect
register
LVIS: Low-
voltage
detection level
select register
Details of
Function
−
The wait time after the STOP mode is released does not include the time from the
release of the STOP mode to the start of clock oscillation (“a” in the figure below),
regardless of whether STOP mode was released by reset signal generation or
interrupt generation.
The oscillation stabilization time that elapses on power application or after release
of reset is selected by the option byte. For details, refer to CHAPTER 15
OPTION BYTE.
Because an interrupt request signal is used to clear the standby mode, if there is
an interrupt source with the interrupt request flag set and the interrupt mask flag
clear, the standby mode is immediately cleared if set.
Because an interrupt request signal is used to clear the standby mode, if there is
an interrupt source with the interrupt request flag set and the interrupt mask flag
reset, the standby mode is immediately cleared if set. Thus, in the STOP mode,
the normal operation mode is restored after the STOP instruction is executed and
then the operation is stopped for 34
stabilizing the oscillation set by the oscillation stabilization time select register
(OSTS) has elapsed when crystal/ceramic oscillation is used).
For an external reset, input a low level for 2
During reset signal generation, the system clock and low-speed internal
oscillation clock stop oscillating.
When the RESET pin is used as an input-only port pin (P34), the 78K0S/KY1+ is
reset if a low level is input to the RESET pin after reset is released by the POC
circuit and before the option byte is referenced again. The reset status is retained
until a high level is input to the RESET pin.
The LVI circuit is not reset by the internal reset signal of the LVI circuit.
The watchdog timer is also reset in the case of an internal reset of the watchdog
timer.
Do not read data by a 1-bit memory manipulation instruction.
If an internal reset signal is generated in the POC circuit, the reset control flag
register (RESF) is cleared to 00H.
Because the detection voltage (V
V, use a voltage in the range of 2.2 to 5.5 V.
In a system where the supply voltage (V
vicinity of the POC detection voltage (V
and released from the reset status. In this case, the time from release of reset to
the start of the operation of the microcontroller can be arbitrarily set by taking the
following action.
To stop LVI, follow either of the procedures below.
Be sure to set bits 2 to 6 to 0.
Bits 4 to 7 must be set to 0.
• When using 8-bit manipulation instruction: Write 00H to LVIM.
• When using 1-bit memory manipulation instruction: Clear LVION to 0.
APPENDIX C LIST OF CAUTIONS
User’s Manual U16994EJ3V0UD
POC
µ
) of the POC circuit is in a range of 2.1 V ±0.1
Cautions
s (TYP.) (after an additional wait time for
POC
DD
) fluctuates for a certain period in the
), the system may be repeatedly reset
µ
s or more to the RESET pin.
p. 178
p. 178
p. 179
p. 182
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p. 186
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p. 189
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