upd78f9211grt2-jjg-a ETC-unknow, upd78f9211grt2-jjg-a Datasheet - Page 68

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upd78f9211grt2-jjg-a

Manufacturer Part Number
upd78f9211grt2-jjg-a
Description
8-bit Single-chip Microcontrollers
Manufacturer
ETC-unknow
Datasheet
CPU clock (f
(2) Low-speed internal oscillation mode register (LSRCM)
68
The fastest instruction of the 78K0S/KY1+ is executed in two CPU clocks. Therefore, the relationship between the
Address: FF58H, After reset: 00H, R/W
Symbol
LSRCM
This register is used to select the operation mode of the low-speed internal oscillator (240 kHz (TYP.)).
This register is valid when it is specified by the option byte that the low-speed internal oscillator can be stopped
by software. If it is specified by the option byte that the low-speed internal oscillator cannot be stopped by
software, setting of this register is invalid, and the low-speed internal oscillator continues oscillating. In addition,
the source clock of WDT is fixed to the low-speed internal oscillator.
WATCHDOG TIMER.
LSRCM can be set by using a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets LSRCM to 00H.
Note The CPU clock (high-speed internal oscillation clock, crystal/ceramic oscillation clock, or external clock
f
f
f
f
f
X
X
X
X
X
/2
/2
/2
/2
2
3
4
CPU Clock (f
CPU
input) is selected by the option byte.
Table 5-2. Relationship between CPU Clock and Minimum Instruction Execution Time
) and the minimum instruction execution time is as shown in Table 5-2.
LSRSTOP
Figure 5-4. Format of Low-Speed internal oscillation Mode Register (LSRCM)
7
0
0
1
CPU
)
Note
Low-speed internal oscillates
Low-speed internal oscillator stops
6
0
0.25
0.5
1.0
2.0
4.0
High-speed internal oscillation clock
µ
µ
µ
µ
µ
s
s
s
s
CHAPTER 5 CLOCK GENERATORS
s
(at 8.0 MHz (TYP.))
5
0
User’s Manual U16994EJ3V0UD
Oscillation/stop of low-speed internal oscillator
Minimum Instruction Execution Time: 2/f
4
0
3
0
0.2
0.4
0.8
1.6
3.2
or external clock input (at 10.0 MHz)
µ
µ
µ
µ
µ
Crystal/ceramic oscillation clock
s
s
s
s
s
2
0
For details, refer to CHAPTER 8
CPU
1
0
LSRSTOP
<0>

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