upd78f9211grt2-jjg-a ETC-unknow, upd78f9211grt2-jjg-a Datasheet - Page 145

• Manufacturer Part Number: upd78f9211grt2-jjg-a
• Description: 8-bit Single-chip Microcontrollers
• Manufacturer: ETC-unknow

8.4.3
low-speed internal oscillation clock is being used.
(1) When the watchdog timer operation clock is the system clock (f
Watchdog timer
CPU operation
The watchdog timer stops counting during STOP instruction execution regardless of whether the system clock or
When STOP instruction is executed, operation of the watchdog timer is stopped. After STOP mode is released,
operation stops for 34
stabilization time select register (OSTS) after operation stops in the case of crystal/ceramic oscillation) and then
counting is started again using the operation clock before the operation was stopped. At this time, the counter is
not cleared to 0 but holds its value.
Note The operation stop time is 17
Watchdog timer operation in STOP mode (when “low-speed internal oscillator can be stopped by
software” is selected by option byte)
Figure 8-6. Operation in STOP Mode (WDT Operation Clock: Clock to Peripheral Hardware)
f
CPU
Watchdog timer
CPU operation
operation
Normal
Operating
<2> CPU clock: High-speed internal oscillation clock or external clock input
f
CPU
µ
s (TYP.) (after waiting for the oscillation stabilization time set by the oscillation
operation
Oscillation stopped
STOP
<1> CPU clock: Crystal/ceramic oscillation clock
Operating
Normal
CHAPTER 8 WATCHDOG TIMER
µ
stopped
Operation stopped
Operation
s (MIN.), 34
User’s Manual U16994EJ3V0UD
Oscillation stopped
Operation stopped
STOP
Note
Oscillation stabilization time
Oscillation stabilization time
µ
s (TYP.), and 67
(set by OSTS register)
stopped
Operation
Note
X
) when the STOP instruction is executed
µ
s (MAX.).
Normal operation
Operating
Normal operation
Operating
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