upd78f9211grt2-jjg-a ETC-unknow, upd78f9211grt2-jjg-a Datasheet - Page 246

• Manufacturer Part Number: upd78f9211grt2-jjg-a
• Description: 8-bit Single-chip Microcontrollers
• Manufacturer: ETC-unknow

16.8.9 Example of internal verify operation in self programming mode
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An example of the internal verify operation in self programming mode is explained below.
<1> Set 01H (internal verify) to the flash program command register (FLCMD).
<2> Set the number of block for which internal verify is performed, to flash address pointer H (FLAPH).
<3> Sets the verify start address to flash address pointer L (FLAPL).
<4> Write the same value as that of FLAPH to the flash address pointer H compare register (FLAPHC).
<5> Sets the verify end address to the flash address pointer L compare register (FLAPLC).
<6> Clear the flash status register (PFS).
<7> Write ACH to the watchdog timer enable register (WDTE) (clear and restart the watchdog timer counter)
<8> Execute the HALT instruction then start self programming. (Execute an instruction immediately after the
<9> Check if a self programming error has occurred using bit 1 (VCERR) and bit 2 (WEPRERR) of PFS.
<10> Internal verify processing is abnormally terminated.
<11> Internal verify processing is normally terminated.
Note This setting is not required when the watchdog timer is not used.
HALT instruction if self programming has been executed.)
Abnormal → <10>
Normal
→ <11>
CHAPTER 16 FLASH MEMORY
User’s Manual U16994EJ3V0UD
Note
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