upd78f9211grt2-jjg-a ETC-unknow, upd78f9211grt2-jjg-a Datasheet - Page 171

• Manufacturer Part Number: upd78f9211grt2-jjg-a
• Description: 8-bit Single-chip Microcontrollers
• Manufacturer: ETC-unknow

10.4 Interrupt Servicing Operation
10.4.1 Maskable interrupt request acknowledgment operation
corresponding interrupt mask flag is cleared to 0. If the interrupt enabled status is in effect (when the IE flag is set to
1), then the request is acknowledged as a vector interrupt.
shown in Table 10-3.
from the interrupt request assigned the highest priority.
Symbol
(4)
A maskable interrupt request can be acknowledged when the interrupt request flag is set to 1 and the
The time required to start the vectored interrupt servicing after a maskable interrupt request has been generated is
See Figures 10-7 and 10-8 for the interrupt request acknowledgment timing.
When two or more maskable interrupt requests are generated at the same time, they are acknowledged starting
A pending interrupt is acknowledged when a status in which it can be acknowledged is set.
PSW
Program status word (PSW)
The program status word is used to hold the instruction execution result and the current status of the interrupt
requests. The IE flag, used to enable and disable maskable interrupts, is mapped to PSW.
PSW can be read- and write-accessed in 8-bit units, as well as using bit manipulation instructions and
dedicated instructions (EI and DI). When a vectored interrupt is acknowledged, the PSW is automatically
saved to a stack, and the IE flag is reset to 0.
Reset signal generation sets PSW to 02H.
Cautions 2. Before setting the INTM0 register, be sure to set the corresponding interrupt mask flag
IE
IE
7
0
1
Table 10-3. Time from Generation of Maskable Interrupt Request to Servicing
Disabled
Enabled
6
Z
(××MK× = 1) to disable interrupts. After setting the INTM0 register, clear the interrupt
request flag (××IF× = 0), then clear the interrupt mask flag (××MK× = 0), which will
enable interrupts.
5
0
Figure 10-5. Program Status Word (PSW) Configuration
Note The wait time is maximum when an interrupt
Remark
9 clocks
AC
4
request is generated immediately before BT and
BF instructions.
Minimum Time
3
0
CHAPTER 10 INTERRUPT FUNCTIONS
1 clock:
Whether to enable/disable interrupt acknowledgment
2
0
User’s Manual U16994EJ3V0UD
f
CPU
1
1
1
(f
CPU
CY
0
: CPU clock)
19 clocks
Maximum Time
After reset
Used in the execution of ordinary instructions
02H
Note
171