upd78f9211grt2-jjg-a ETC-unknow, upd78f9211grt2-jjg-a Datasheet - Page 344

• Manufacturer Part Number: upd78f9211grt2-jjg-a
• Description: 8-bit Single-chip Microcontrollers
• Manufacturer: ETC-unknow

344
Flash
memory
Function
Security
settings
Self
programming
function
FLPMC: Flash
programming
mode control
register
PFCMD: Flash
protect
command
register
FLAPH, FLAPL:
Flash address
pointers H and
L
Details of
Function
After the security setting of the batch erase is set, erasure cannot be performed
for the device. In addition, even if a write command is executed, data different
from that which has already been written to the flash memory cannot be written
because the erase command is disabled.
The security setting is valid when the programming mode is set next time.
Self programming processing must be included in the program before performing
self writing.
No instructions can be executed while a self programming command is being
executed. Therefore, clear and restart the watchdog timer counter in advance so
that the watchdog timer does not overflow during self programming. Refer to
Table 16-11 for the time taken for the execution of self programming.
Interrupts that occur during self programming can be acknowledged after self
programming mode ends. To avoid this operation, disable interrupt servicing (by
setting MK0 to FFH, and executing the DI instruction) before a mode is shifted
from the normal mode to the self programming mode with a specific sequence.
RAM is not used while a self programming command is being executed.
If the supply voltage drops or the reset signal is input while the flash memory is
being written or erased, writing/erasing is not guaranteed.
The value of the blank data set during block erasure is FFH.
When the oscillator or the external clock is selected as the main clock, a wait time
of 16
execution of the HALT instruction.
The state of the pins in self programming mode is the same as that in HALT
mode.
Since the security function set via on-board/off-board programming is disabled in
self programming mode, the self programming command can be executed
regardless of the security function setting. To disable write or erase processing
during self programming, set the protect byte.
Be sure to clear bits 4 to 7 of flash address pointer H (FLAPH) and flash address
pointer H compare register (FLAPHC) to 0 before executing the self programming
command. If the value of these bits is 1 when executing the self programming
command.
Cautions in the case of setting the self programming mode, refer to 16.8.2
Cautions on self programming function.
When the oscillator or the external clock is selected as the main clock, a wait time
of 16
Disable interrupt servicing (by setting MK0 to FFH and executing the DI
instruction) while the specific sequence is under execution.
Be sure to clear bits 4 to 7 of flash address pointer H (FLAPH) and flash address
pointer H compare register (FLAPHC) to 0 before executing the self programming
command. If the value of these bits is 1 when executing the self programming
command.
µ
µ
s is required starting from the setting of the self programming mode to the
s is required from setting FLSPM to 1 to execution of the HALT instruction.
APPENDIX C LIST OF CAUTIONS
User’s Manual U16994EJ3V0UD
Cautions
p. 220
p. 220
p. 221
p. 224
p. 224
p. 224
p. 224
p. 224
p. 224
p. 224
p. 224
p. 224
p. 225
p. 225
p. 225
p. 229
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