upd78f9211grt2-jjg-a ETC-unknow, upd78f9211grt2-jjg-a Datasheet - Page 335

• Manufacturer Part Number: upd78f9211grt2-jjg-a
• Description: 8-bit Single-chip Microcontrollers
• Manufacturer: ETC-unknow

16-bit
timer/
event
counters
00
Function
CR010: 16-bit
capture/
compare
register 010
TMC00: 16-bit
timer mode
control register
00
CRC00:
Capture/
compare control
register 00
TOC00: 16-bit
timer output
control register
00
Details of
Function
If the register read period and the input of the capture trigger conflict when CR010
is used as a capture register, the capture trigger input takes precedence and the
read data is undefined. Also, if the timer count stop and the input of the capture
trigger conflict, the capture data is undefined.
Changing the CR010 setting during TM00 operation may cause a malfunction. To
change the setting, refer to 6.5 Cautions Related to 16-Bit Timer/Event Counter
00 (17) Changing compare register during timer operation.
16-bit timer counter 00 (TM00) starts operation at the moment TMC002 and
TMC003 (operation stop mode) are set to a value other than 0, 0, respectively.
Set TMC002 and TMC003 to 0, 0 to stop the operation.
The timer operation must be stopped before writing to bits other than the OVF00
flag.
If the timer is stopped, timer counts and timer interrupts do not occur, even if a
signal is input to the TI000/TI010 pins.
Except when TI000 pin valid edge is selected as the count clock, stop the timer
operation before setting STOP mode or system clock stop mode; otherwise the
timer may malfunction when the system clock starts.
Set the valid edge of the TI000 pin with bits 4 and 5 of prescaler mode register 00
(PRM00) after stopping the timer operation.
If the clear & start mode entered on a match between TM00 and CR000, clear &
start mode at the valid edge of the TI000 pin, or free-running mode is selected,
when the set value of CR000 is FFFFH and the TM00 value changes from FFFFH
to 0000H, the OVF00 flag is set to 1.
Even if the OVF00 flag is cleared before the next count clock is counted (before
TM00 becomes 0001H) after the occurrence of a TM00 overflow, the OVF00 flag
is re-set newly and clear is disabled.
The capture operation is performed at the fall of the count clock. An interrupt
request input (INTTM0n0), however, occurs at the rise of the next count clock.
The timer operation must be stopped before setting CRC00.
When the clear & start mode entered on a match between TM00 and CR000 is
selected by 16-bit timer mode control register 00 (TMC00), CR000 should not be
specified as a capture register.
To ensure the reliability of the capture operation, the capture trigger requires a
pulse longer than two cycles of the count clock selected by prescaler mode
register 00 (PRM00) (refer to Figure 6-17).
Timer operation must be stopped before setting other than OSPT00.
If LVS00 and LVR00 are read, 0 is read.
OSPT00 is automatically cleared after data is set, so 0 is read.
Do not set OSPT00 to 1 other than in one-shot pulse output mode.
A write interval of two cycles or more of the count clock selected by prescaler
mode register 00 (PRM00) is required, when OSPT00 is set to 1 successively.
When the TOE00 is 0, set the TOE00, LVS00, and LVR00 at the same time with
the 8-bit memory manipulation instruction. When the TOE00 is 1, the LVS00 and
LVR00 can be set with the 1-bit memory manipulation instruction.
APPENDIX C LIST OF CAUTIONS
User’s Manual U16994EJ3V0UD
Cautions
pp. 85,
117
p. 86
pp. 86,
115
pp. 87,
116
pp. 87,
115
pp. 87,
120
pp. 87,
116
p. 87
pp. 87,
117
pp. 87,
118
pp. 88,
116
pp. 88,
115
pp. 88,
118
pp. 89,
116
pp. 89,
116
pp. 89,
116
pp. 89,
116
pp. 89,
116
p. 90
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