upd78f9211grt2-jjg-a ETC-unknow, upd78f9211grt2-jjg-a Datasheet - Page 186

• Manufacturer Part Number: upd78f9211grt2-jjg-a
• Description: 8-bit Single-chip Microcontrollers
• Manufacturer: ETC-unknow

programs at the address written in addresses 0000H and 0001H when the reset signal is generated.
circuit voltage detection, and each item of hardware is set to the status shown in Table 14-1. Each pin is high
impedance during reset signal generation or during the oscillation stabilization time just after reset release, except for
P130, which is low-level output.
reset is released and the CPU starts program execution after referencing the option byte (after the option byte is
referenced and the clock oscillation stabilization time elapses if crystal/ceramic oscillation is selected). A reset
generated by the watchdog timer source is automatically released after the reset, and the CPU starts program
execution after referencing the option byte (after the option byte is referenced and the clock oscillation stabilization
time elapses if crystal/ceramic oscillation is selected). (see Figures 12-2 to 12-4). Reset by POC and LVI circuit
power supply detection is automatically released when V
program execution after referencing the option byte (after the option byte is referenced and the clock oscillation
stabilization time elapses if crystal/ceramic oscillation is selected) (see CHAPTER 13 POWER-ON-CLEAR CIRCUIT
and CHAPTER 14 LOW-VOLTAGE DETECTOR).
186
The following four operations are available to generate a reset signal.
(1) External reset input via RESET pin
(2) Internal reset by watchdog timer overflows
(3) Internal reset by comparison of supply voltage and detection voltage of power-on-clear (POC) circuit
(4) Internal reset by comparison of supply voltage and detection voltage of low-power-supply detector (LVI)
External and internal resets have no functional differences. In both cases, program execution starts from the
A reset is applied when a low level is input to the RESET pin, the watchdog timer overflows, or by POC and LVI
When a low level is input to the RESET pin, a reset occurs, and when a high level is input to the RESET pin, the
Cautions 1. For an external reset, input a low level for 2
2. During reset signal generation, the system clock and low-speed internal oscillation clock
3. When the RESET pin is used as an input-only port pin (P34), the 78K0S/KY1+ is reset if a low
stop oscillating.
level is input to the RESET pin after reset is released by the POC circuit and before the option
byte is referenced again. The reset status is retained until a high level is input to the RESET
pin.
CHAPTER 12 RESET FUNCTION
User’s Manual U16994EJ3V0UD
DD
> V
POC
µ
s or more to the RESET pin.
or V
DD
> V
LVI
after the reset, and the CPU starts