upd78f9211grt2-jjg-a ETC-unknow, upd78f9211grt2-jjg-a Datasheet - Page 340

• Manufacturer Part Number: upd78f9211grt2-jjg-a
• Description: 8-bit Single-chip Microcontrollers
• Manufacturer: ETC-unknow

340
A/D
Converter
Function
Operating
current in STOP
mode
Input range of
ANI0 to ANI3
Conflicting
operations
Noise
countermeasures
ANI0/P20 to
ANI3/P23
ANI0/P20 to
ANI3/P23
Input
impedance of
ANI0 to ANI3
pins
Details of
Function
The A/D converter stops operating in the STOP mode. At this time, the operating
current can be reduced by clearing bit 7 (ADCS) and bit 0 (ADCE) of the A/D
converter mode register (ADM) to 0.
Observe the rated range of the ANI0 to ANI3 input voltage. If a voltage of AV
or higher and V
input to an analog input channel, the converted value of that channel becomes
undefined. In addition, the converted values of the other channels may also be
affected.
Conflict between A/D conversion result register (ADCR, ADCRH) write and
ADCR, ADCRH read by instruction upon the end of conversion ADCR, ADCRH
read has priority. After the read operation, the new conversion result is written to
ADCR, ADCRH.
Conflict between ADCR, ADCRH write and A/D converter mode register (ADM)
write or analog input channel specification register (ADS) write upon the end of
conversion ADM or ADS write has priority. ADCR, ADCRH write is not
performed, nor is the conversion end interrupt signal (INTAD) generated.
To maintain the 10-bit resolution, attention must be paid to noise input to the
AV
<1> Connect a capacitor with a low equivalent resistance and a high frequency
<2> Because the effect increases in proportion to the output impedance of the
<3> Do not switch the A/D conversion function of the ANI0 to ANI3 pins to their
<4> The conversion accuracy can be improved by setting HALT mode
The analog input pins (ANI0 to ANI3) are also used as input port pins (P20 to
P23).
When A/D conversion is performed with any of ANI0 to ANI3 selected, do not
access P20 to P23 while conversion is in progress; otherwise the conversion
resolution may be degraded.
If a digital pulse is applied to the pins adjacent to the pins currently used for A/D
conversion, the expected value of the A/D conversion may not be obtained due to
coupling noise. Therefore, do not apply a pulse to the pins adjacent to the pin
undergoing A/D conversion.
In this A/D converter, the internal sampling capacitor is charged and sampling is
performed during sampling time.
Since only the leakage current flows other than during sampling and the current
for charging the capacitor also flows during sampling, the input impedance
fluctuates both during sampling and otherwise.
If the shortest conversion time of the reference voltage is used, to perform
sufficient sampling, it is recommended to make the output impedance of the
analog input source 1 kΩ or lower, or attach a capacitor of around 0.01
µ
F to the ANI0 to ANI3 pins (see Figure 9-19).
REF
analog input source, it is recommended that a capacitor be connected
externally, as shown in Figure 9-19, to reduce noise.
alternate functions during conversion.
immediately after the conversion starts.
response to the power supply.
pin and ANI0 to ANI3 pins.
APPENDIX C LIST OF CAUTIONS
User’s Manual U16994EJ3V0UD
SS
or lower (even in the range of absolute maximum ratings) is
Cautions
µ
F to 0.1
REF
p. 163
p. 163
p. 163
p. 163
p. 163
p. 164
p. 164
p. 164
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