upd78f9211grt2-jjg-a ETC-unknow, upd78f9211grt2-jjg-a Datasheet - Page 228

• Manufacturer Part Number: upd78f9211grt2-jjg-a
• Description: 8-bit Single-chip Microcontrollers
• Manufacturer: ETC-unknow

228
(5) Flash address pointers H and L (FLAPH and FLAPL)
These registers are used to specify the start address of the flash memory when the memory is erased, written,
or verified in the self-programming mode.
FLAPH and FLAPL consist of counters, and they are incremented until the values match with those of
FLAPHC and FLAPLC when the programming command is not executed. When the programming command
is executed, therefore, set the value again.
These registers are set with a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation makes these registers undefined.
Note If a value other than the above is set and the self programming mode is set, the self programming
Address: FFA3H
Symbol
FLCMD
mode is canceled immediately and no execution occurs. At this time, the flag of the PFS register is
not set.
Figure 16-15. Format of Flash Programming Command Register (FLCMD)
FLCMD2
7
0
0
0
1
1
Other than above
After reset: 00H
FLCMD1
6
0
0
1
0
0
CHAPTER 16 FLASH MEMORY
FLCMD0
Note
User’s Manual U16994EJ3V0UD
5
0
1
1
0
1
R/W
Setting prohibited
Internal verify
Block erase
Block blank check
Byte write
Command Name
4
0
3
0
This command is used to check if
data has been correctly written to the
flash memory. After data has been
written to the memory, execute this
command by specifying a block
number, start address, and end
address.
(VCERR) or bit 2 (WEPRERR) of the
flash status register (PFS) is set to 1.
This command is used to erase
specified block. It is used both in the
on-board
programming mode.
This command is used to check if the
specified block has been erased.
This command is used to write 1-byte
data to the specified address in the
flash memory.
address and write data, then execute
this command.
If 1 is written to a bit that has not
been erased (a bit for which the data
is 0), then bit 2 (WEPRERR) of the
flash status register (PFS) becomes
1.
FLCMD2
2
If an error occurs, bit 1
mode
Function
FLCMD1
Specify the write
1
and
FLCMD0
0
self-