upd78f9211grt2-jjg-a ETC-unknow, upd78f9211grt2-jjg-a Datasheet - Page 348

• Manufacturer Part Number: upd78f9211grt2-jjg-a
• Description: 8-bit Single-chip Microcontrollers
• Manufacturer: ETC-unknow

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Modification of Figure 9-1. Timing of A/D Converter Sampling and A/D Conversion
Modification of Table 9-1. Sampling Time and A/D Conversion Time and Note 1
Modification of Figure 9-3. Format of A/D Converter Mode Register (ADM) and Note 2
Modification of (6) Input impedance of ANI0 to ANI3 pins in 9.6 Cautions for A/D Converter
Modification of 10.1 Interrupt Function Types
Modification of 10.4.2 Multiple interrupt servicing
Addition of Caution to Example 1 in Figure 10-9. Example of Multiple Interrupts (1/2)
Addition of Example 3 to Figure 10-9. Example of Multiple Interrupts (1/2)
Modification of reset signal in Figure 11-3. HALT Mode Release by Reset Signal Generation
Modification of description in External interrupt of Table 11-4. Operating Statuses in STOP Mode
Modification of description in and addition of Note to (a) Release by unmasked interrupt request in (2) of
11.2.2 STOP mode
Modification of reset signal in Figure 11-6. STOP Mode Release by Reset Signal Generation
Modification of Figure 12-1. Block Diagram of Reset Function
Addition of delay time of internal reset signal generation to Figure 12-2. Timing of Reset by RESET Input
and Figure 12-4. Reset Timing by RESET Input in STOP Mode
Modification of Figure 13-3. Example of Software Processing After Release of Reset (1/2)
Modification of Figure 14-1. Block Diagram of Low-Voltage Detector
Modification of Note 1 in Figure 14-2. Format of Low-Voltage Detect Register (LVIM)
Modification of Note in Figure 14-3. Format of Low-Voltage Detection Level Select Register (LVIS)
Modification of INTLVI and Note 2 in Figure 14-5. Timing of Low-Voltage Detector Interrupt Signal
Generation
Modification of (2) in <Action> of 14.5 Cautions for Low-Voltage Detector
Modification of Figure 14-6. Example of Software Processing After Release of Reset (1/2)
Modification of description and configuration in CHAPTER 15 OPTION BYTE
Modification of Caution in Figure 15-2. Format of Option Byte (1/2)
Addition of Remark 3, 4 to Figure 15-2. Format of Option Byte (2/2)
Modification of and addition to 16.1 Features
Figure 16-2. Environment for Writing Program to Flash Memory is divided into two figures, in the case of
FlashPro4 and in the case of PG-FPL2
Modification of Caution in Table 16-5. Oscillation Frequency and PG-FP4 GUI Software Setting Value
Example
Deletion of 16.7.1 Flash memory programming mode
Modification of 16.7.2 Communication commands
Modification of and Addition to 16.8.2 Cautions on self programming function
Addition of <Setting conditions> in 3. Operating conditions of WEPRERR flag of 16.8.3 Registers used
for self programming function (3)
Addition of description to Figure 16-15. Format of Flash Programming Command Register (FLCMD)
Modification of Caution in Figure 16-16. Format of Flash Address Pointer H/L (FLAPH/FLAPL)
Modification of Caution 2 in Figure 16-17. Format of Flash Address Pointer H/L Compare Registers
(FLAPHC/FLAPLC)
APPENDIX D REVISION HISTORY
User’s Manual U16994EJ3V0UD
Description
(2/3)