upd78f9211grt2-jjg-a ETC-unknow, upd78f9211grt2-jjg-a Datasheet - Page 185

• Manufacturer Part Number: upd78f9211grt2-jjg-a
• Description: 8-bit Single-chip Microcontrollers
• Manufacturer: ETC-unknow

(b) Release by reset signal generation
System clock
When the reset signal is input, STOP mode is released and a reset operation is performed after the
oscillation stabilization time has elapsed.
Note Operation is stopped (277
Reset signal
Note Operation is stopped (276
Remark f
System clock
CPU status
Reset signal
oscillation
CPU status
oscillation
(1) If CPU clock is high-speed internal oscillation clock or external input clock
referenced.
referenced.
×: don’t care
Maskable interrupt request
Reset signal generation
Table 11-5. Operation in Response to Interrupt Request in STOP Mode
X
: System clock oscillation frequency
Release Source
Figure 11-6. STOP Mode Release by Reset signal generation
Oscillation
Operation
Operation
Oscillation
mode
mode
(2) If CPU clock is crystal/ceramic oscillation clock
instruction
instruction
STOP
STOP
CHAPTER 11 STANDBY FUNCTION
STOP mode
STOP mode
User’s Manual U16994EJ3V0UD
µ
µ
s (MIN.), 544
s (MIN.), 544
MK××
0
0
1
−
Oscillation stops.
Oscillation stops.
IE
0
1
×
×
µ
µ
s (TYP.), 1.075 ms (MAX.)) because the option byte is
s (TYP.), 1.074 ms (MAX.)) because the option byte is
period
Reset
period
Reset
Next address instruction execution
Interrupt servicing execution
STOP mode held
Reset processing
Operation
stops
Operation
stops
Note
Operation
Note
Oscillation stabilization time
.
.
stabilization waits
Oscillation
(2
10
Oscillation
Operation mode
/f
Oscillation
X
to 2
17
/f
X
)
Operation
mode
185