upd78f9211grt2-jjg-a ETC-unknow, upd78f9211grt2-jjg-a Datasheet - Page 96

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upd78f9211grt2-jjg-a

Manufacturer Part Number
upd78f9211grt2-jjg-a
Description
8-bit Single-chip Microcontrollers
Manufacturer
ETC-unknow
Datasheet
96
Note OVF00 is 1 only when 16-bit timer capture/compare register 000 is set to FFFFH.
Caution When reading the external event counter count value, TM00 should be read.
Valid edge of TI000
TM00 count value
TM00 count value
TI000 pin input
TI000 pin input
INTTM000
INTTM000
Figure 6-17. External Event Counter Operation Timing (with Rising Edge Specified)
CR000
CR000
f
XP
(2) INTTM000 generation timing after INTTM000 has been generated twice
(1) INTTM000 generation timing immediately after operation starts
N
Noise eliminator
Figure 6-16. External Event Counter Configuration Diagram
Timer operation starts
Counting is started after a valid edge is detected twice.
1
0000H 0001H 0002H 0003H 0004H
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00
2
0000H 0001H 0002H 0003H
Count starts
3
User’s Manual U16994EJ3V0UD
N
N
16-bit timer counter 00 (TM00)
16-bit timer capture/compare
register 000 (CR000)
Internal bus
N–1
N–2
Match
N–1
N
Clear
0000H 0001H 0002H 0003H
N
0000H 0001H 0002H
OVF00
Note
INTTM000

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