upd78f9211grt2-jjg-a ETC-unknow, upd78f9211grt2-jjg-a Datasheet - Page 117

• Manufacturer Part Number: upd78f9211grt2-jjg-a
• Description: 8-bit Single-chip Microcontrollers
• Manufacturer: ETC-unknow

(12) One-shot pulse output with external trigger
(13) Operation of OVF00 flag
(14) Conflicting operations
<3> Do not set the 16-bit timer capture/compare registers 000 and 010 (CR000 and CR010) to 0000H.
<1> Do not input the external trigger again while the one-shot pulse is output.
<2> Do not set the 16-bit timer capture/compare registers 000 and 010 (CR000 and CR010) to 0000H.
<1> The OVF00 flag is also set to 1 in the following case.
<2> Even if the OVF00 flag is cleared before the next count clock is counted (before TM00 becomes 0001H)
If the register read period and the input of the capture trigger conflict when CR000/CR010 is used as a capture
register, the capture trigger input takes precedence and the read data is undefined. Also, if the count stop of
the timer and the input of the capture trigger conflict, the captured data is undefined.
To output the one-shot pulse again, wait until the current one-shot pulse output is completed.
Either of the clear & start mode entered on a match between TM00 and CR000, clear & start at the valid
edge of the TI000 pin, or free-running mode is selected.
When TM00 is counted up from FFFFH to 0000H.
after the occurrence of a TM00 overflow, the OVF00 flag is reset newly and clear is disabled.
CR000 is set to FFFFH.
↓
↓
Count clock
INTTM000
OVF00
CR000
TM00
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00
Figure 6-38. Operation Timing of OVF00 Flag
FFFEH
FFFFH
User’s Manual U16994EJ3V0UD
FFFFH
0000H
0001H
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