upd78f9211grt2-jjg-a ETC-unknow, upd78f9211grt2-jjg-a Datasheet - Page 337

• Manufacturer Part Number: upd78f9211grt2-jjg-a
• Description: 8-bit Single-chip Microcontrollers
• Manufacturer: ETC-unknow

16-bit
timer/
event
counters
00
Function
PPG output
One-shot pulse
output: software
trigger
One-shot pulse
output: external
trigger
Timer start
errors
One-shot pulse
output
Capture
operation
Changing
compare
register during
timer operation
External event
counter
Details of
Function
The cycle of the pulse generated through PPG output (CR000 setting value + 1)
has a duty of (CR010 setting value + 1)/(CR000 setting value + 1).
Do not set the OSPT00 bit to 1 again while the one-shot pulse is being output. To
output the one-shot pulse again, wait until the current one-shot pulse output is
completed.
When using the one-shot pulse output of 16-bit timer/event counter 00 with a
software trigger, do not change the level of the TI000 pin or its alternate-function
port pin. Because the external trigger is valid even in this case, the timer is
cleared and started even at the level of the TI000 pin or its alternate-function port
pin, resulting in the output of a pulse at an undesired timing.
Do not set 0000H to the CR000 and CR010 registers.
16-bit timer counter 00 starts operating as soon as a value other than 00
(operation stop mode) is set to the TMC003 and TMC002 bits.
Do not input the external trigger again while the one-shot pulse is output. To
output the one-shot pulse again, wait until the current one-shot pulse output is
completed.
Do not set the CR000 and CR010 registers to 0000H.
16-bit timer counter 00 starts operating as soon as a value other than 00
(operation stop mode) is set to the TMC002 and TMC003 bits.
An error of up to one clock may occur in the time required for a match signal to be
generated after timer start. This is because 16-bit timer counter 00 (TM00) is
started asynchronously to the count clock.
One-shot pulse output normally operates only in the free-running mode or in the
clear & start mode at the valid edge of the TI000 pin. Because an overflow does
not occur in the clear & start mode on a match between TM00 and CR000, one-
shot pulse output is not possible.
When the CRC001 bit value is 1, capture is not performed in the CR000 register if
both the rising and falling edges have been selected as the valid edges of the
TI000 pin.
When the CRC001 bit value is 1, the TM00 count value is not captured in the
CR000 register when a valid edge of the TI010 pin is detected, but the input from
the TI010 pin can be used as an external interrupt source because INTTM000 is
generated at that timing.
With the 16-bit timer capture/compare register 0n0 (CR0n0) used as a compare
register, when changing CR0n0 around the timing of a match between 16-bit timer
counter 00 (TM00) and 16-bit timer capture/compare register 0n0 (CR0n0) during
timer counting, the change timing may conflict with the timing of the match, so the
operation is not guaranteed in such cases. To change CR0n0 during timer
counting, INTTM000 interrupt servicing performs the following operation.
If CR010 is changed during timer counting without performing processing <1>
above, the value in CR010 may be rewritten twice or more, causing an inversion
of the output level of the TO00 pin at each rewrite.
The timing of the count start is after two valid edge detections.
APPENDIX C LIST OF CAUTIONS
User’s Manual U16994EJ3V0UD
Cautions
pp. 108,
120
pp. 110,
116
pp. 110,
116
pp. 111,
113
pp. 112,
115
pp. 112,
117
pp. 113,
117
pp. 114,
115
p. 115
p. 116
p. 118
p. 118
p. 119
p. 119
p. 120
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