upd78f9211grt2-jjg-a ETC-unknow, upd78f9211grt2-jjg-a Datasheet - Page 181

• Manufacturer Part Number: upd78f9211grt2-jjg-a
• Description: 8-bit Single-chip Microcontrollers
• Manufacturer: ETC-unknow

(b) Release by reset signal generation
System clock
When the reset signal is input, HALT mode is released, and then, as in the case with a normal reset
operation, the program is executed after branching to the reset vector address.
Note Operation is stopped (277
Note Operation is stopped (276
Remark f
Reset signal
System clock
Reset signal
CPU status
CPU status
oscillation
(1) When CPU clock is high-speed internal oscillation clock or external input clock
oscillation
referenced.
referenced.
×: don’t care
Maskable interrupt request
Reset signal generation
Table 11-3. Operation in Response to Interrupt Request in HALT Mode
X
: System clock oscillation frequency
Release Source
Figure 11-3. HALT Mode Release by Reset Signal Generation
Operation
Operation
(2) When CPU clock is crystal/ceramic oscillation clock
mode
mode
instruction
instruction
HALT
HALT
Oscillates
Oscillates
CHAPTER 11 STANDBY FUNCTION
HALT mode
HALT mode
User’s Manual U16994EJ3V0UD
µ
µ
s (MIN.), 544
s (MIN.), 544
MK××
0
0
1
−
IE
0
1
×
×
µ
µ
s (TYP.), 1.075 ms (MAX.)) because the option byte is
s (TYP.), 1.074 ms (MAX.)) because the option byte is
period
Oscillation stops
Reset
period
Reset
Oscillation stops
Next address instruction execution
Interrupt servicing execution
HALT mode held
Reset processing
Operation
stops
Operation
stops
Note
Oscillation stabilization time
Operation
Note
stabilization waits
(2
Oscillation
10
/f
Operation mode
Oscillates
X
to 2
Oscillates
17
/f
X
)
Operation
mode
181