upd78f9211grt2-jjg-a ETC-unknow, upd78f9211grt2-jjg-a Datasheet - Page 184

• Manufacturer Part Number: upd78f9211grt2-jjg-a
• Description: 8-bit Single-chip Microcontrollers
• Manufacturer: ETC-unknow

184
Note Only when sets count clock to f
(a) Release by unmasked interrupt request
Note The operation stop time is 17
Remark The broken lines indicate the case when the interrupt request that has released the standby mode
When an unmasked interrupt request (8-bit timer H1, low-voltage detector, external interrupt request) is
generated, the STOP mode is released. After the oscillation stabilization time has elapsed, if interrupt
acknowledgment is enabled, vectored interrupt servicing is carried out. If interrupt acknowledgment is
disabled, the next address instruction is executed.
Standby release
Standby release
System clock
System clock
CPU status
oscillation
CPU status
(1) If CPU clock is high-speed internal oscillation clock or external input clock
is acknowledged.
signal
signal
Figure 11-5. STOP Mode Release by Interrupt Request Generation
Oscillation
Oscillation
Operation
Operation
(2) If CPU clock is crystal/ceramic oscillation clock
mode
mode
instruction
instruction
STOP
STOP
CHAPTER 11 STANDBY FUNCTION
RL
/2
µ
7
s (MIN.), 34
User’s Manual U16994EJ3V0UD
STOP mode
STOP mode
Oscillation stops.
Oscillation stops.
Interrupt
request
Interrupt
request
µ
s (TYP.), and 67
Operation
stops
Operation
stops
Note
Note
Oscillation stabilization time
.
.
Waiting for stabilization
(HALT mode status)
µ
(set by OSTS)
of oscillation
s (MAX.).
Operation mode
Oscillation
Oscillation
Operation
mode