upd78f9211grt2-jjg-a ETC-unknow, upd78f9211grt2-jjg-a Datasheet - Page 170

• Manufacturer Part Number: upd78f9211grt2-jjg-a
• Description: 8-bit Single-chip Microcontrollers
• Manufacturer: ETC-unknow

170
Address: FFE4H
Address: FFECH
Symbol
Symbol
INTM0
MK0
(2)
(3) External interrupt mode register 0 (INTM0)
Interrupt mask flag register 0 (MK0)
The interrupt mask flag is used to enable and disable the corresponding maskable interrupts.
MK0 is set with a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets MK0 to FFH.
This register is used to set the valid edge of INTP0 and INTP1.
INTM0 is set with an 8-bit memory manipulation instruction.
Reset signal generation clears INTM0 to 00H.
Caution Because P21 and P32 have an alternate function as external interrupt inputs, when the
Cautions 1. Be sure to clear bits 0, 1, 6, and 7 to 0.
××MK×
ES11
ES01
ADMK
<7>
0
0
1
1
7
0
0
0
1
1
0
1
After reset: FFH
After reset: 00H
output level is changed by specifying the output mode of the port function, an interrupt
request flag is set. Therefore, the interrupt mask flag should be set to 1 before using the
output mode.
ES10
ES00
TMMK010 TMMK000 TMMKH1
Enables interrupt servicing.
Disables interrupt servicing.
6
0
0
1
0
1
0
1
0
1
<6>
Figure 10-4. Format of External Interrupt Mode Register 0 (INTM0)
Figure 10-3. Format of Interrupt Mask Flag Register 0 (MK0)
Falling edge
Rising edge
Setting prohibited
Both rising and falling edges
Falling edge
Rising edge
Setting prohibited
Both rising and falling edges
ES11
5
<5>
R/W
R/W
ES10
CHAPTER 10 INTERRUPT FUNCTIONS
4
<4>
User’s Manual U16994EJ3V0UD
ES01
3
PMK1
<3>
ES00
Interrupt servicing control
2
INTP1 valid edge selection
INTP0 valid edge selection
PMK0
<2>
1
0
LVIMK
<1>
0
0
1
0