upd78f9211grt2-jjg-a ETC-unknow, upd78f9211grt2-jjg-a Datasheet - Page 153

• Manufacturer Part Number: upd78f9211grt2-jjg-a
• Description: 8-bit Single-chip Microcontrollers
• Manufacturer: ETC-unknow

Note The time from the rising of the ADCE bit to the rising of the ADCS bit must be 1
Cautions 1. The above sampling time and conversion time do not include the clock frequency error.
Notes 3. Set the sampling time as follows.
internal circuit.
ADCS
2. If a bit other than ADCS of ADM is manipulated while A/D conversion is stopped (ADCS = 0)
3. A/D conversion must be stopped (ADCS = 0) before rewriting bits FR0 to FR2.
4. Be sure to clear bits 6, 2, and 1 to 0.
Comparator
margin maximum of ±5% when using the high-speed internal oscillator).
0
0
1
4. Set the A/D conversion time as follows.
5. The operation of the comparator is controlled by ADCS and ADCE, and it takes 1
Select the conversion time taking the clock frequency error into consideration (an error
and then A/D conversion is started, execute two NOP instructions or an instruction
equivalent to two machine cycles, and set ADCS to 1.
ADCE
ADCS
• V
• V
• V
• V
• V
• V
• V
• V
operation start to operation stabilization. Therefore, when ADCS is set to 1 after 1
has elapsed from the time ADCE is set to 1, the conversion result at that time has priority over
the first conversion result. If the ADCS is set to 1 without waiting for 1
first conversion data.
DD
DD
DD
DD
DD
DD
DD
DD
ADCE
≥ 4.5 V:
≥ 4.0 V:
≥ 2.85 V:
≥ 2.7 V:
≥ 4.5 V:
≥ 4.0 V:
≥ 2.85 V:
≥ 2.7 V:
0
1
×
Figure 9-4. Timing Chart When Comparator Is Used
Note
Stop status (DC power consumption path does not exist)
Conversion waiting mode (only comparator consumes power)
Conversion mode
Table 9-2. Settings of ADCS and ADCE
Conversion
operation
1.0
2.4
3.0
11.0
3.0
4.8
6.0
14.0
CHAPTER 9 A/D CONVERTER
µ
µ
µ
µ
µ
µ
µ
µ
s or more
s or more
s or more
s or more and less than 100
s or more and less than 100
s or more and less than 100
Comparator operating
User’s Manual U16994EJ3V0UD
s or more
s or more and less than 100
Conversion
waiting
A/D Conversion Operation
Conversion
operation
µ
µ
µ
µ
s
s
s
s
Conversion stopped
µ
s or longer to stabilize the
µ
s or longer, ignore the
µ
s or more
µ
s from
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