upd78f9211grt2-jjg-a ETC-unknow, upd78f9211grt2-jjg-a Datasheet - Page 244

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upd78f9211grt2-jjg-a

Manufacturer Part Number
upd78f9211grt2-jjg-a
Description
8-bit Single-chip Microcontrollers
Manufacturer
ETC-unknow
Datasheet
244
Note This setting is not required when the watchdog timer is not used.
Remark
<1> to <10> in Figure 16-24 correspond to <1> to <10> in 16.8.8 (previous page).
Figure 16-24. Example of Byte Write Operation in Self Programming Mode
<4> Set data to be written to FLW
<6> Clear & restart WDT counter
<3> Set address at which data
<1> Set byte write command
<7> Execute HALT instruction
<2> Set no. of block to be
is to be written, to FLAPL
<10> Normal termination
(VCERR and WEPRERR flags)
<8> Check execution result
(WDTE = ACH)
written, to FLAPH
(FLCMD = 05H)
<5> Clear PFS
Byte write
CHAPTER 16 FLASH MEMORY
Normal
User’s Manual U16994EJ3V0UD
Note
Abnormal
<9> Abnormal termination

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