upd78f9211grt2-jjg-a ETC-unknow, upd78f9211grt2-jjg-a Datasheet - Page 225

• Manufacturer Part Number: upd78f9211grt2-jjg-a
• Description: 8-bit Single-chip Microcontrollers
• Manufacturer: ETC-unknow

(2) Flash protect command register (PFCMD)
Caution Disable interrupt servicing (by setting MK0 to FFH and executing the DI instruction) while the
If the application system stops inadvertently due to malfunction caused by noise or program hang-up, an
Writing FLPMC is enabled only when a write operation is performed in the following specific sequence.
<1> Write a specific value to PFCMD (A5H)
<2> Write the value to be set to bit 0 (FLSPM) of the FLPMC (writing in this step is invalid)
<3> Write the inverted value of the value to be set to bit 0 (FLSPM) of the FLPMC (writing in this step is
<4> Write the value to be set to bit 0 (FLSPM) of the FLPMC (writing in this step is valid)
This rewrites the value of the register, so that the register cannot be written illegally.
Occurrence of an illegal store operation can be checked by bit 0 (FPRERR) of the flash status register (PFS).
A5H must be written to PFCMD each time the value of FLPMC is changed.
PFCMD can be set by an 8-bit memory manipulation instruction.
Reset signal generation makes PFCMD undefined.
operation to write the flash programming mode control register (FLPMC) may have a serious effect on the
system. PFCMD is used to protect FLPMC from being written, so that the application system does not stop
inadvertently.
Address: FFA2H
Symbol
FLPMC
invalid)
Figure 16-12. Format of Flash Programming Mode Control Register (FLPMC)
specific sequence is under execution.
Notes 1. Bit 0 (FLSPM) is cleared to 0 when reset is released. The set value of the protect
Cautions 1. Cautions in the case of setting the self programming mode, refer to 16.8.2
PRSELF4 PRSELF3 PRSELF2 PRSELF1 PRSELF0 The set value of the protect byte
FLSPM
7
0
0
1
2. Bits 2 to 6 (PRSELF0 to PRSELF4) are read-only.
After reset: Undefined
2. When the oscillator or the external clock is selected as the main clock, a wait
byte is read to bits 2 to 6 (PRSELF0 to PRSELF4) after reset is released.
Normal mode
Self-programming mode
PRSELF4 PRSELF3 PRSELF2 PRSELF1 PRSELF0
Flash memory instructions can be fetched from all addresses.
Before executing the HALT instruction, set the command, address offset, write
data, and set FLSPM to 1.
instruction; the flash memory mode is then shifted from the normal mode to the
flash memory programming mode.
Cautions on self programming function.
time of 16
instruction.
6
CHAPTER 16 FLASH MEMORY
Selection of operation mode during self-programming mode
User’s Manual U16994EJ3V0UD
µ
5
s is required from setting FLSPM to 1 to execution of the HALT
Note 1
4
R/W
Note 2
After setting these items, execute the HALT
3
is read to these bits.
2
1
0
FLSPM
0
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