upd78f9211grt2-jjg-a ETC-unknow, upd78f9211grt2-jjg-a Datasheet - Page 177

• Manufacturer Part Number: upd78f9211grt2-jjg-a
• Description: 8-bit Single-chip Microcontrollers
• Manufacturer: ETC-unknow

set are held. The I/O port output latches and output buffer statuses are also held.
(2) STOP mode
In either of these two modes, all the contents of registers, flags and data memory just before the standby mode is
Cautions 1. When shifting to the STOP mode, be sure to stop the peripheral hardware operation before
STOP instruction execution sets the STOP mode. In the STOP mode, the system clock oscillator stops,
stopping the whole system, thereby considerably reducing the CPU operating current.
Because this mode can be cleared by an interrupt request, it enables intermittent operations to be carried out.
However, select the HALT mode if processing must be immediately started by an interrupt request when the
operation stop time
stabilizing oscillation elapses when crystal/ceramic oscillation is used).
Note
2. The following sequence is recommended for operating current reduction of the A/D converter
3. If the low-speed internal oscillator is operating before the STOP mode is set, oscillation of the
executing STOP instruction (except the peripheral hardware that operates on the low-speed
internal oscillation clock).
when the standby function is used: First clear bit 7 (ADCS) and bit 0 (ADCE) of the A/D
converter mode register (ADM) to 0 to stop the A/D conversion operation, and then execute
the HALT or STOP instruction.
low-speed internal oscillation clock cannot be stopped in the STOP mode (refer to Table 11-1).
The operation stop time is 17
Note
is generated after the STOP mode is released (because an additional wait time for
CHAPTER 11 STANDBY FUNCTION
User’s Manual U16994EJ3V0UD
µ
s (MIN.), 34
µ
s (TYP.), and 67
µ
s (MAX.).
177