upd78f9211grt2-jjg-a ETC-unknow, upd78f9211grt2-jjg-a Datasheet - Page 338

• Manufacturer Part Number: upd78f9211grt2-jjg-a
• Description: 8-bit Single-chip Microcontrollers
• Manufacturer: ETC-unknow

338
8-bit timer
H1
Watchdog
timer
Function
CMP01: 8-bit
timer H
compare
register 01
CMP11: 8-bit
timer H
compare
register 11
TMHMD1: 8-bit
timer H mode
register 1
PWM output
WDTM:
Watchdog timer
mode register
WDTE:
Watchdog timer
enable register
Details of
Function
CMP01 cannot be rewritten during timer count operation.
In the PWM output mode, be sure to set CMP11 when starting the timer count
operation (TMHE1 = 1) after the timer count operation was stopped (TMHE1 = 0)
(be sure to set again even if setting the same value to CMP11).
When TMHE1 = 1, setting the other bits of the TMHMD1 register is prohibited.
In the PWM output mode, be sure to set 8-bit timer H compare register 11
(CMP11) when starting the timer count operation (TMHE1 = 1) after the timer
count operation was stopped (TMHE1 = 0) (be sure to set again even if setting the
same value to the CMP11 register).
In PWM output mode, the setting value for the CMP11 register can be changed
during timer count operation. However, three operation clocks (signal selected
using the CKS12 to CKS10 bits of the TMHMD1 register) or more are required to
transfer the register value after rewriting the CMP11 register value.
Be sure to set the CMP11 register when starting the timer count operation
(TMHE1 = 1) after the timer count operation was stopped (TMHE1 = 0) (be sure
to set again even if setting the same value to the CMP11 register).
Make sure that the CMP11 register setting value (M) and CMP01 register setting
value (N) are within the following range.
Set bits 7, 6, and 5 to 0, 1, and 1, respectively. Do not set the other values.
After reset is released, WDTM can be written only once by an 8-bit memory
manipulation instruction. If writing is attempted a second time, an internal reset
signal is generated. However, at the first write, if “1” and “x” are set for WDCS4
and WDCS3 respectively and the watchdog timer is stopped, then the internal
reset signal does not occur even if the following are executed.
WDTM cannot be set by a 1-bit memory manipulation instruction.
When using the flash memory self programming by self writing, set the overflow
time for the watchdog timer so that enough everflow time is secured (Example 1-
byte writing: 200
If a value other than ACH is written to WDTE, an internal reset signal is
generated.
If a 1-bit memory manipulation instruction is executed for WDTE, an internal reset
signal is generated.
The value read from WDTE is 9AH (this differs from the written value (ACH)).
• Second write to WDTM
• 1-bit memory manipulation instruction to WDTE
• Writing of a value other than “ACH” to WDTE
00H ≤ CMP11 (M) < CMP01 (N) ≤ FFH
APPENDIX C LIST OF CAUTIONS
User’s Manual U16994EJ3V0UD
µ
s MIN., 1-block deletion: 10 ms MIN.).
Cautions
p. 123
p. 123
p. 125
p. 125
p. 131
p. 131
p. 131
p. 139
p. 140
p. 140
p. 140
p. 140
p. 140
p. 140
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