upd78f9211grt2-jjg-a ETC-unknow, upd78f9211grt2-jjg-a Datasheet - Page 130

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upd78f9211grt2-jjg-a

Manufacturer Part Number
upd78f9211grt2-jjg-a
Description
8-bit Single-chip Microcontrollers
Manufacturer
ETC-unknow
Datasheet
7.4.2
during timer operation is prohibited.
during timer operation is possible.
CMP01 register match after the timer count is started. TOH1 output becomes inactive when 8-bit timer counter H1
and the CMP11 register match.
(1) Usage
130
TMHMD1
In PWM output mode, a pulse with an arbitrary duty and arbitrary cycle can be output.
8-bit timer compare register 01 (CMP01) controls the cycle of timer output (TOH1). Rewriting the CMP01 register
8-bit timer compare register 11 (CMP11) controls the duty of timer output (TOH1). Rewriting the CMP11 register
The operation in PWM output mode is as follows.
TOH1 output becomes active and 8-bit timer counter H1 is cleared to 0 when 8-bit timer counter H1 and the
<1> Set each register.
In PWM output mode, a pulse for which an arbitrary duty and arbitrary cycle can be set is output.
<2> The count operation starts when TMHE1 = 1.
<3> The CMP01 register is the compare register that is to be compared first after count operation is enabled.
Operation as PWM output mode
(i) Setting timer H mode register 1 (TMHMD1)
(ii) Setting CMP01 register
(iii) Setting CMP11 register
When the values of 8-bit timer counter H1 and the CMP01 register match, 8-bit timer counter H1 is cleared,
an interrupt request signal (INTTMH1) is generated, and TOH1 output becomes active. At the same time,
the compare register to be compared with 8-bit timer counter H1 is changed from the CMP01 register to the
CMP11 register.
TMHE1
0
• Compare value (N): Cycle setting
• Compare value (M): Duty setting
Remark 00H ≤ CMP11 (M) < CMP01 (N) ≤ FFH
CKS12
0/1
CKS11
Figure 7-9. Register Setting in PWM Output Mode
0/1
CKS10
0/1
CHAPTER 7 8-BIT TIMER H1
User’s Manual U16994EJ3V0UD
TMMD11
1
TMMD10 TOLEV1
0
0/1
TOEN1
1
Timer output enabled
Timer output level inversion setting
PWM output mode selection
Count clock (f
Count operation stopped
CNT
) selection

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