upd78f9211grt2-jjg-a ETC-unknow, upd78f9211grt2-jjg-a Datasheet - Page 272

• Manufacturer Part Number: upd78f9211grt2-jjg-a
• Description: 8-bit Single-chip Microcontrollers
• Manufacturer: ETC-unknow

272
Remark
CMP
ADDW
SUBW
CMPW
INC
DEC
INCW
DECW
ROR
ROL
RORC
ROLC
SET1
CLR1
SET1
CLR1
NOT1
Mnemonic
One instruction clock cycle is one CPU clock cycle (f
(PCC).
A, #byte
saddr, #byte
A, r
A, saddr
A, !addr16
A, [HL]
A, [HL + byte]
AX, #word
AX, #word
AX, #word
r
saddr
r
saddr
rp
rp
A, 1
A, 1
A, 1
A, 1
saddr.bit
sfr.bit
A.bit
PSW.bit
[HL].bit
saddr.bit
sfr.bit
A.bit
PSW.bit
[HL].bit
CY
CY
CY
Operand
CHAPTER 17 INSTRUCTION SET OVERVIEW
Bytes
2
3
2
2
3
1
2
3
3
3
2
2
2
2
1
1
1
1
1
1
3
3
2
3
2
3
3
2
3
2
1
1
1
User’s Manual U16994EJ3V0UD
Clocks
10
10
4
6
4
4
8
6
6
6
6
6
4
4
4
4
4
4
2
2
2
2
6
6
4
6
6
6
4
6
2
2
2
A − byte
(saddr) − byte
A − r
A − (saddr)
A − (addr16)
A − (HL)
A − (HL + byte)
AX, CY ← AX + word
AX, CY ← AX − word
AX − word
r ← r + 1
(saddr) ← (saddr) + 1
r ← r − 1
(saddr) ← (saddr) − 1
rp ← rp + 1
rp ← rp − 1
(CY, A
(CY, A
(CY ← A
(CY ← A
(saddr.bit) ← 1
sfr.bit ← 1
A.bit ← 1
PSW.bit ← 1
(HL).bit ← 1
(saddr.bit) ← 0
sfr.bit ← 0
A.bit ← 0
PSW.bit ← 0
(HL).bit ← 0
CY ← 1
CY ← 0
CY ← CY
7
0
CPU
← A
← A
0
7
, A
, A
) selected by the processor clock control register
0
7
7
0
, A
, A
← CY, A
← CY, A
m−1
m+1
← A
← A
Operation
m−1
m+1
m
m
) × 1
) × 1
← A
← A
m
m
) × 1
) × 1
Z
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
Flag
AC CY
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
1
0
×