upd78f9211grt2-jjg-a ETC-unknow, upd78f9211grt2-jjg-a Datasheet - Page 156

• Manufacturer Part Number: upd78f9211grt2-jjg-a
• Description: 8-bit Single-chip Microcontrollers
• Manufacturer: ETC-unknow

9.4
9.4.1
156
<1> Select one channel for A/D conversion using the analog input channel specification register (ADS).
<2> Set ADCE to 1 and wait for 1
<3> Execute two NOP instructions or an instruction equivalent to two machine cycles.
<4> Set ADCS to 1 and start the conversion operation.
<5> The voltage input to the selected analog input channel is sampled by the sample & hold circuit.
<6> When sampling has been done for a certain time, the sample & hold circuit is placed in the hold state and the
<7> Bit 9 of the successive approximation register (SAR) is set. The D/A converter voltage tap is set to (1/2) V
<8> The voltage difference between the D/A converter voltage tap and analog input is compared by the voltage
<9> Next, bit 8 of SAR is automatically set to 1, and the operation proceeds to the next comparison. The D/A
<10> Comparison is continued in this way up to bit 0 of SAR.
<11> Upon completion of the comparison of 10 bits, an effective digital result value remains in SAR, and the result
<12> Repeat steps <5> to <11>, until ADCS is cleared to 0.
Cautions 1. Make sure the period of <1> to <4> is 1
Remark The following two types of A/D conversion result registers can be used.
A/D Converter Operations
Basic operations of A/D converter
(<5> to <11> are operations performed by hardware.)
input analog voltage is held until the A/D conversion operation has ended.
by the tap selector.
comparator. If the analog input is greater than (1/2) AV
input is smaller than (1/2) V
converter voltage tap is selected according to the preset value of bit 9, as described below.
• Bit 9 = 1: (3/4) V
• Bit 9 = 0: (1/4) V
The voltage tap and analog input voltage are compared and bit 8 of SAR is manipulated as follows.
• Analog input voltage ≥ Voltage tap: Bit 8 = 1
• Analog input voltage < Voltage tap: Bit 8 = 0
value is transferred to the A/D conversion result register (ADCR, ADCRH) and then latched.
At the same time, the A/D conversion end interrupt request (INTAD) can also be generated.
To stop the A/D converter, clear ADCS to 0.
To restart A/D conversion from the status of ADCE = 1, start from <3>. To restart A/D conversion from the
status of ADCE = 0, start from <2>.
<1> ADCR (16 bits): Stores a 10-bit A/D conversion value.
<2> ADCRH (8 bits): Stores an 8-bit A/D conversion value.
2.
It is no problem if the order of <1> and <2> is reversed.
DD
DD
DD
µ
, the MSB is reset to 0.
s or longer.
CHAPTER 9 A/D CONVERTER
User’s Manual U16994EJ3V0UD
µ
s or more.
DD
, the MSB of SAR remains set to 1. If the analog
DD