upd78f9211grt2-jjg-a ETC-unknow, upd78f9211grt2-jjg-a Datasheet - Page 350

• Manufacturer Part Number: upd78f9211grt2-jjg-a
• Description: 8-bit Single-chip Microcontrollers
• Manufacturer: ETC-unknow

D.2 Revision History up to Previous Editions
each edition in which the revision was applied.
350
2nd edition
The following table shows the revision history up to this edition. The “Applied to:” column indicates the chapters of
Edition
Addition of settings for port mode register 4 (PM4) when using 78K0S/KU1+
Deletion of high-speed internal oscillation mode register (HSRCM)
Modification of Type36 in Figure 2-1 Pin I/O Circuits
Addition of Note 4 to Table 3-3 Special Function Registers (1/2)
Addition of Part Number to 1.3 Ordering Information
Addition of Remarks 1, 2 in Table 4-1 Port Functions
Addition of Figure 4-3 Block Diagram of P22
Modification of operation stop time in the following figures.
• Figure 5-8 Timing Chart of Default Start by High-Speed internal Oscillator
• Figure 5-10 Timing Chart of Default Start by Crystal/Ceramic Oscillator
• Figure 5-12 Timing of Default Start by External Clock Input
Addition of Cautions to 6.2 Configuration of 16-Bit Timer/Event Counter 00 (1) 16-bit
timer counter 00 (TM00), (2) 16-bit timer capture/compare register 000 (CR000), and
(3) 16-bit timer capture/compare register 010 (CR010)
Addition of Cautions in Figure 6-5 Format of 16-Bit Timer Mode Control Register 00
(TMC00)
Addition of Caution 6 to Figure 6-7 Format of 16-Bit Timer Output Control Register
00 (TOC00)
Modification of Caution 3 and addition of Caution 4 in Figure 6-8 Format of Prescaler
Mode Register 00 (PRM00)
Addition of (1) INTTM000 generation timing immediately after operation starts : The
setting value +2 of CR000 to 1 Figure 6-17 External Event Counter Operation Timing
(with Rising Edge Specified)
Modification of Note in Figure 6-24 Control Register Settings for Pulse Width
Measurement with Free-Running Counter and Two Capture Registers (with Rising
Edge Specified)
Modification and addition to 6.5 Cautions Related to 16-Bit Timer/Event Counter 00
Modification of Table 8-1 Loop Detection Time of Watchdog Timer
Addition of Caution 4 and modification to Figure 8-2 Format of Watchdog Timer Mode
Register (WDTM)
Modification of Figure 8-4 Status Transition Diagram When “Low-Speed Internal
Oscillator Cannot Be Stopped” Is Selected by Option Byte
Modification of Figure 8-5 Status Transition Diagram When “Low-Speed Internal
Oscillator Can Be Stopped by Software” Is Selected by Option Byte
Modification of operation stop time in the following figures
• Figure 8-6 Operation in STOP Mode (WDT Operation Clock: Clock to Peripheral
Hardware)
• Figure 8-7 Operation in STOP Mode (WDT Operation Clock: Low-Speed Internal
Oscillation Clock)
APPENDIX D REVISION HISTORY
User’s Manual U16994EJ3V0UD
Description
Throughout
CHAPTER 1
OVERVIEW
CHAPTER 2 PIN
FUNCTIONS
CHAPTER 3 CPU
ARCHITECTURE
CHAPTER 4 PORT
FUNCTIONS
CHAPTER 5 CLOCK
GENERATORS
CHAPTER 6 16-BIT
TIMER/EVENT
COUNTER 00
CHAPTER 8
WATCHDOG TIMER
Applied to:
(1/3)