upd78f9211grt2-jjg-a ETC-unknow, upd78f9211grt2-jjg-a Datasheet - Page 333

• Manufacturer Part Number: upd78f9211grt2-jjg-a
• Description: 8-bit Single-chip Microcontrollers
• Manufacturer: ETC-unknow

This appendix lists cautions described in this document.
“Classification (hard/soft)” in table is as follows.
Hard:
Soft:
Pin
functions
Memory
space
Port
functions
Main clock
Function
Cautions for microcontroller internal/external hardware
Cautions for software such as register settings or programs
P22/X2/ANI2,
P23/X1/ANI3
SP: stack
pointer
P22/X2/ANI2,
P23/X1/ANI3
P34
P21, P32
OSTS:
Oscillation
stabilization
time select
register
Details of
Function
−
The P22/X2/ANI2, P23/X1/ANI3 pins are pulled down during reset.
Since reset signal generation makes the SP contents undefined, be sure to
initialize the SP before using the stack memory.
The P22/X2/ANI2, P23/X1/ANI3 pins are pulled down during reset.
Because the P34 pin functions alternately as the RESET pin, if it is used as an
input port pin, the function to input an external reset signal to the RESET pin
cannot be used. The function of the port is selected by the option byte. For
details, refer to CHAPTER 15 OPTION BYTE.
Also, since the option byte is referenced after the reset release, if low level is
input to the RESET pin before the referencing, then the reset state is not
released. When it is used as an input port pin, connect the pull-up resistor.
Because P21 and P32 are also used as external interrupt pins, the
corresponding interrupt request flag is set if each of these pins is set to the
output mode and its output level is changed. To use the port pin in the output
mode, therefore, set the corresponding interrupt mask flag to 1 in advance.
Although a 1-bit memory manipulation instruction manipulates 1 bit, it accesses
a port in 8-bit units. Therefore, the contents of the output latch of a pin in the
input mode, even if it is not subject to manipulation by the instruction, are
undefined in a port with a mixture of inputs and outputs.
To set and then release the STOP mode, set the oscillation stabilization time as
follows.
Expected oscillation stabilization time of resonator ≤ Oscillation stabilization
time set by OSTS
The wait time after the STOP mode is released does not include the time from
the release of the STOP mode to the start of clock oscillation (“a” in the figure
below), regardless of whether STOP mode was released by reset input or
interrupt generation.
The oscillation stabilization time that elapses on power application or after
release of reset is selected by the option byte. For details, refer to CHAPTER
15 OPTION BYTE.
APPENDIX C LIST OF CAUTIONS
User’s Manual U16994EJ3V0UD
Cautions
pp. 21,
p. 36
p. 51
p. 57
p. 59
p. 63
p. 69
p. 69
p. 69
22, 23, 24
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