upd78f9211grt2-jjg-a ETC-unknow, upd78f9211grt2-jjg-a Datasheet - Page 179

• Manufacturer Part Number: upd78f9211grt2-jjg-a
• Description: 8-bit Single-chip Microcontrollers
• Manufacturer: ETC-unknow

11.2 Standby Function Operation
11.2.1 HALT mode
Note
Item
System clock
CPU
Port (latch)
16-bit timer/event counter 00
8-bit timer
H1
Watchdog
timer
A/D converter
Power-on-clear circuit
Low-voltage detector
External interrupt
(1) HALT mode
The HALT mode is set by executing the HALT instruction.
The operating statuses in the HALT mode are shown below.
Caution Because an interrupt request signal is used to clear the standby mode, if there is an interrupt
“Cannot be stopped” or “Stopped by software” is selected for low-speed internal oscillator by the option byte
(for the option byte, see CHAPTER 15 OPTION BYTE).
Sets count clock to f
Sets count clock to f
“System clock” selected as
operating clock
“Low-speed internal oscillation
clock” selected as operating
clock
source with the interrupt request flag set and the interrupt mask flag clear, the standby mode
is immediately cleared if set.
Setting of HALT Mode
XP
RL
/2
to f
Table 11-2. Operating Statuses in HALT Mode
7
XP
/2
12
CHAPTER 11 STANDBY FUNCTION
Operation stops.
Holds status before HALT mode was set.
Operable
Operable
Operable
Setting disabled.
Operable
(Operation continues)
Always operates.
Operable
Operable
Clock supply to CPU is stopped.
Operable
User’s Manual U16994EJ3V0UD
Oscillator cannot be
Low-Speed Internal
stopped
Note
.
Operable
Operation stops.
Operation stops.
When Low-Speed Internal
Oscillation Continues
Low-Speed Internal Oscillator can be stopped
Operation stops.
When Low-Speed Internal
Oscillation Stops
Note
179
.