upd78f9211grt2-jjg-a ETC-unknow, upd78f9211grt2-jjg-a Datasheet - Page 93

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upd78f9211grt2-jjg-a

Manufacturer Part Number
upd78f9211grt2-jjg-a
Description
8-bit Single-chip Microcontrollers
Manufacturer
ETC-unknow
Datasheet
Remark 0/1: Setting 0 or 1 allows another function to be used simultaneously with the interval timer. See the
Note OVF00 is set to 1 only when 16-bit timer capture/compare register 000 is set to FFFFH.
TI000/ANI0/
PRM00
CRC00
TMC00
TOH1/P20
f
f
XP
XP
ES110
/2
/2
f
XP
0/1
2
8
7
0
7
0
description of the respective control registers for details.
ES100
0/1
Noise
eliminator
6
0
6
0
Figure 6-11. Control Register Settings for Interval Timer Operation
f
XP
ES010
0/1
5
0
5
0
ES000
Figure 6-12. Interval Timer Configuration Diagram
(a) 16-bit timer mode control register 00 (CRC00)
(c) 16-bit timer mode control register 00 (TMC00)
0/1
4
0
4
0
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00
(b) Prescaler mode register 00 (PRM00)
TMC003
3
0
3
0
1
CRC002
TMC002
0/1
User’s Manual U16994EJ3V0UD
2
0
1
CRC001
TMC001
PRM001
16-bit timer capture/compare
register 000 (CR000)
0/1
0/1
0/1
16-bit timer counter 00
(TM00)
CRC000
OVF00
PRM000
0/1
0
0
CR000 used as compare register
Selects count clock.
Setting invalid (setting “10” is prohibited.)
Setting invalid (setting “10” is prohibited.)
Clears and starts on match between TM00 and CR000.
OVF00
Note
Clear
circuit
INTTM000
93

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