upd78f9211grt2-jjg-a ETC-unknow, upd78f9211grt2-jjg-a Datasheet - Page 193

• Manufacturer Part Number: upd78f9211grt2-jjg-a
• Description: 8-bit Single-chip Microcontrollers
• Manufacturer: ETC-unknow

12.1 Register for Confirming Reset Source
store which source has generated the reset request.
Many internal reset generation sources exist in the 78K0S/KY1+. The reset control flag register (RESF) is used to
RESF can be read by an 8-bit memory manipulation instruction.
RESET input, reset signal generation by power-on-clear (POC) circuit, and reading RESF clear RESF to 00H.
The status of RESF when a reset request is generated is shown in Table 12-2.
Address: FF54H
Symbol
RESF
Flag
WDTRF
LVIRF
Note The value after reset varies depending on the reset source.
Caution Do not read data by a 1-bit memory manipulation instruction.
WDTRF
LVIRF
7
0
0
1
0
1
After reset: 00H
Reset Source
Table 12-2. RESF Status When Reset Request Is Generated
Figure 12-5. Format of Reset Control Flag Register (RESF)
Internal reset request is not generated, or RESF is cleared.
Internal reset request is generated.
Internal reset request is not generated, or RESF is cleared.
Internal reset request is generated.
6
0
Note
Cleared (0)
RESET Input
CHAPTER 12 RESET FUNCTION
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User’s Manual U16994EJ3V0UD
5
0
Internal reset request by low-voltage detector (LVI)
Internal reset request by watchdog timer (WDT)
WDTRF
Cleared (0)
Reset by POC
4
3
0
Set (1)
Held
Reset by WDT
2
0
Held
Set (1)
Reset by LVI
1
0
LVIRF
0
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