cx28224 Mindspeed Technologies, cx28224 Datasheet - Page 100

• Manufacturer Part Number: cx28224
• Description: Cx28224/5/9 Inverse Multiplexing For The Atm Ima Family
• Manufacturer: Mindspeed Technologies

General Issues
6.1.2.3
6-6
Interrupt Servicing
When an interrupt occurs on the MicroInt* pin (pin B19), it could have been
generated by any of 128 events. The CX2822x’s interrupt indication structure ensures
that no more than a maximum of three register reads are needed to determine the
source of an interrupt. The interrupt is traced back to its source using the following
steps:
All Level 1 bits are cleared when the register is read. Once the register is read, ALL
bits in that register are reset to their default values. Therefore, interrupt service
routines must be designed to handle multiple interrupts in the same registers. In Level
2, OneSecInt and ExInt are cleared when the register is read. However, the TxCellInt
and RxCellInt bits are cleared only when the corresponding Level 1 register is read
and cleared. Level 3 bits are cleared when the entire corresponding Level 2 register
has been read and cleared.
1.
2.
3.
Read the SUMPORT register to see which port(s) shows an interrupt.
Read the appropriate SUMINT register to see which bit(s) shows an interrupt.
If necessary, read the appropriate TXCELLINT or RXCELLINT register.
Bit 0, RxCellInt, reflects activity in the RXCELLINT register.
Bit 1, TxCellInt, reflects activity in the TXCELLINT register.
Bit 2, ExInt, indicates an interrupt from an external framer.
Bit 3, OneSecInt, indicates a one-second interrupt.
Bits 4–7 are reserved.
Mindspeed Technologies
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CX28224/5/9 Data Sheet
28229-DSH-001-D