cx28224 Mindspeed Technologies, cx28224 Datasheet - Page 189

• Manufacturer Part Number: cx28224
• Description: Cx28224/5/9 Inverse Multiplexing For The Atm Ima Family
• Manufacturer: Mindspeed Technologies

CX28224/5/9 Data Sheet
28229-DSH-001-D
Bit
7
6
5
4
3
2
1
0
Default
0
0
0
0
0
0
0
0
0x51F—IMA_GRP_5TO8_SEM (Group Table Control II (CX28229 Only))
Update Enable for Receive group 8
Update Enable for Receive group 7
Update Enable for Receive group 6
Update Enable for Receive group 5
Update Enable for Transmit group 8
Update Enable for Transmit group 7
Update Enable for Transmit group 6
Update Enable for Transmit group 5
For the following bits, 1 = the group table is being updated, 0 = the group table is not
being updated. The update enable must be set to 1 prior to writing the group table. All
elements of the group table must be re-written. After writing to all 8 elements, the
update enable is reset to 0. The group tables are described below.
NOTE:
Name
This register cannot be read back.
Mindspeed Technologies
addresses 0x5DC–0x5DF (Not defined for CX28224 and CX28225)
addresses 0x5D8–0x5DB (Not defined for CX28224 and CX28225)
addresses 0x5D4–0x5D7 (Not defined for CX28224 and CX28225)
addresses 0x5D0–0x5D3 (Not defined for CX28224 and CX28225)
addresses 0x538–0x53F (Not defined for CX28224 and CX28225)
addresses 0x530–0x537 (Not defined for CX28224 and CX28225)
addresses 0x528–0x52F (Not defined for CX28224 and CX28225)
addresses 0x520–0x527 (Not defined for CX28224 and CX28225)
™
Description
Registers
7
-
89