cx28224 Mindspeed Technologies, cx28224 Datasheet - Page 23

• Manufacturer Part Number: cx28224
• Description: Cx28224/5/9 Inverse Multiplexing For The Atm Ima Family
• Manufacturer: Mindspeed Technologies

CX28224/5/9 Data Sheet
1.1.5
Table 1-4. Memory Requirements for Differential Delay (in bytes)
28229-DSH-001-D
GENERAL NOTE:
Number of ports
16
32
1
2
4
8
Shaded areas can be supported by internal memory. Internal memory is disabled when the external bus is used.
Differential Delay
E1
T1
When dealing with multiple facilities, there is no guarantee that the individual links
within a group will take the same physical path between the terminating equipment.
This variation is referred to as Differential Delay. The ATM Forum specification
requires an IMA implementation to absorb a minimum of 25 ms of differential delay
between the links. Each port requires 8 K of memory for every 27.5 ms of delay (at
E1; 8 K provides for 34.375 ms at T1 rates). The CX28229 provides 256K bytes of
on-board memory for the buffering necessary to re-align the links within an IMA
group. This is sufficient to support the 25 ms delay for 32 IMA ports. In addition, an
external memory bus allows this to be expanded to 2 MB, which supports up to 200
ms of delay.
The magnitude of the differential delay can be quite large when dealing with T1/E1
links; whereas DSL links generally follow the same path and have nearly identical
delays.
128 K
256 K
34.375 ms
16 K
32 K
64 K
8 K
27.5 ms
Table 1-4
Mindspeed Technologies
shows the memory requirements for differential delay.
68.75 ms
55 ms
128 K
256 K
512 K
16 K
32 K
64 K
™
137.5 ms
110 ms
1024 K
128 K
256 K
512 K
32 K
64 K
Introduction to IMA
220 ms
275 ms
1024 K
2048 K
128 K
256 K
512 K
64 K
1
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9