cx28224 Mindspeed Technologies, cx28224 Datasheet - Page 96

• Manufacturer Part Number: cx28224
• Description: Cx28224/5/9 Inverse Multiplexing For The Atm Ima Family
• Manufacturer: Mindspeed Technologies

General Issues
6.1.2
6.1.2.1
6-2
Counters (TC Block Only)
The CX2822x counters record events within the TC block. Two types of events are
recorded: error events, such as Section BIP errors, and transmission events, such as
transmitted ATM cells.
Counters comprised of more than one register must be accessed by reading the least
significant byte (LSB) first. This guarantees that the value contained in each
component register accurately reflects the composite counter value at the time the
LSB was read, because the counter may be updated while the component registers are
being read.
Each counter is large enough to accommodate the maximum number of events that
may occur within a one-second interval. The counters are cleared after being read.
Therefore, if the counters are read every second, the application will receive an
accurate recording of all events.
One-second Latching
The CX2822x’s implementation of one-second latching ensures the integrity of the
statistics being gathered by the network management software. Internal statistics
counters can be latched at one-second intervals, which are synchronized to the
OneSecIO pin (pin R5). Therefore, the data read from the statistic counters represents
the same one second of real-time data, independent of network management software
timing.
The CX2822x implements one-second latching for both status signals and counter
values. When the EnStatLat bit (bit 5) in the MODE register (0x0202) is written to a
logical 1, a read from any of the status registers returns the state of the device at the
time of the previous OneSecIO pin (pin R5) assertion. When the EnCntrLat bit (bit 4)
in the MODE register (0x0202) is written to a logical 1, a read from any of the
counters returns the state of the device at the time of the previous OneSecIO pin (pin
R5) assertion. Every second, the counter is read, moved to the latch, and the counter is
cleared. The latch is cleared when read.
Software can configure the OneSecIO pin as an output that equals the input from the
8kHzIn divided by 8000. When configured as an input, status registers and counters
may be latched on the rising edge of this input. See Bit 0 of the Mode register
(0x200).
NOTE:
When latching is disabled and a counter is wider than one byte, the LSB
should be read first to retain the values of the other bytes for a
subsequent read.
Mindspeed Technologies
™
CX28224/5/9 Data Sheet
28229-DSH-001-D