cx28224 Mindspeed Technologies, cx28224 Datasheet - Page 199

• Manufacturer Part Number: cx28224
• Description: Cx28224/5/9 Inverse Multiplexing For The Atm Ima Family
• Manufacturer: Mindspeed Technologies

CX28224/5/9 Data Sheet
28229-DSH-001-D
Group 1–16 Address
Group 1–16 Address
0x440 0x442 0x444 0x446 0x540 0x542 0x544 0x546 0x640 0x642 0x644 0x646 0x740 0x742 0x744 0x746
0x441 0x443 0x445 0x447 0x541 0x543 0x545 0x547 0x641 0x643 0x645 0x647 0x741 0x743 0x745 0x747
n=1
n=1
7-0
7-0
CX28224
Bit
CX28224
Bit
n=2
n=2
CX28225
CX28225
Default
Default
0
0
n=3
n=3
IMA_TX_GRPn_CELL_COUNT_LSB (Transmit Cell Count LSBs)
IMA_TX_GRPn_CELL_COUNT_MSB (Transmit Cell Count MSBs)
Transmit Cell Count LSBs
Transmit Cell Count MSBs
n=4
n=4
This register contains the least significant bits of a 16 bit count of the number of ATM
layer cells transmitted over the Transmit links within the group. The register is read
only. Status clears upon read.
This register contains the most significant bits of a 16 bit count of the number of ATM
layer cells transmitted over the Transmit links within the group. The register is read
only. Status clears upon read.
n=5
n=5
Name
Name
n=6
n=6
Mindspeed Technologies
n=7
n=7
Transmit Group Cell Count: This field contains the least significant bits of a
16-bit count of the number of ATM layer cells transmitted over the Transmit
links within the group. A write operation with data = 0x01 to the first address
(0x440 for Group #1, 0x442 for Group #2, etc.) transfers the state of all 16
bits of the counter to registers that are accessible to the microprocessor bus
and clears the state of the counter, The first address should be read first. The
second address (0x441 for Group #1, 0x443 for Group #2, etc.) is read next.
A write operation with data = 0x00 to the first address of each group returns
back to the raw counters.
Transmit Group Cell Count: This field contains the most significant
bits of a 16 bit count of the number of ATM layer cells transmitted
over the Transmit links within the group. A write operation
0x01
etc.) transfers the state of all 16 bits of the counter to registers that
are accessible to the microprocessor bus and clears the counter. A
read operation should then be performed to read the previous state of
the counter. The first address should be read first. The second address
(0x441 for Group #1, 0x443 for Group #2, etc.) is read next.
operation with data = 0x00 to the first address of each group returns back to
the raw counters.
to the first address (0x440 for Group #1, 0x442 for Group #2,
n=8
n=8
CX28229
CX28229
Not Applicable
Not Applicable
n=9
n=9
Not Applicable
Not Applicable
n=10
n=10
™
n=11
n=11
Description
Description
n=12
n=12
n=13
n=13
n=14
n=14
n=15
n=15
with data =
A write
Registers
n=16
n=16
7
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99