cx28224 Mindspeed Technologies, cx28224 Datasheet - Page 141

• Manufacturer Part Number: cx28224
• Description: Cx28224/5/9 Inverse Multiplexing For The Atm Ima Family
• Manufacturer: Mindspeed Technologies

CX28224/5/9 Data Sheet
28229-DSH-001-D
FOOTNOTE:
(1)
Bit
Bit
The default for these bits is the port number for each port. (000—Port 0, 001—Port 1, 010—Port 2, 011—Port 3, 100—Port 4,
101—Port 5, 110—Port 6, 111—Port 7)
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Default
Default
(1)
(1)
(1)
0
0
0
0
0
0
0
0
0
0
0
0
0
0x0F—UDF2 (UDF2 Control Register)
0x10—TXHDR1 (Transmit Cell Header Control Register 1)
UDF2[7]
UDF2[6]
UDF2[5]
UDF2[4]
UDF2[3]
UDF2[2]
UDF2[1]
UDF2[0]
TxHdr1[7]
TxHdr1[6]
TxHdr1[5]
TxHdr1[4]
TxHdr1[3]
TxHdr1[2]
TxHdr1[1]
TxHdr1[0]
The contents of the UDF2 register are inserted into the UDF2 byte on the UTOPIA
receive bus when operating in 16-bit UTOPIA mode.
The TXHDR1 register contains the first byte of the Transmit Cell Header. It controls
the header value that is inserted in the transmitted cell. This header consists of 32 bits
divided among four registers (TXHDR1–4).
Name
Name
Mindspeed Technologies
The contents of this register are output over the UTOPIA receive bus when operating
in UTOPIA 16-bit mode. The default matches the port address.
These bits hold the Transmit Header values for Octet 1 of the outgoing cell. Insertion
of the bits is controlled by the HDRFIELD register (0x09).
GFC/VPI bits
(for UNI they are GFC bits, for NNI they are VPI bits)
VPI bits
Description
Description
™
Registers
7
-
41