cx28224 Mindspeed Technologies, cx28224 Datasheet - Page 64

• Manufacturer Part Number: cx28224
• Description: Cx28224/5/9 Inverse Multiplexing For The Atm Ima Family
• Manufacturer: Mindspeed Technologies

CX2822x Hardware Description
2.6
Figure 2-9. Far-End Line Loopback (This only shows the TC Block.)
2-36
SPRxSync
SPTxSync
SPRxData
SPRxHold
SPTxData
SPRxClkI
SPTxClk
Interface
General Note:
Framer
Configuring a port for line loopback mode disables all UTOPIA signals for that port.
(Line)
This segment is replicated for Ports 0 - 7
Loopback
Control
Far-End Line Loopback (Serial Configuration Only)
Far-End Line loopback verifies Line interface is communicating with the PHY. It is
enabled by bit 4 of the PMODE register (0x04). When line loopback is enabled for a
given port, all data received by the CX2822x on that port is processed by the Receive
Line Interface and transmitted out the line interface. Data from the Transmit UTOPIA
bus is ignored.
NOTE:
TC Transmit Port
TC Receive Port
SPTxClk, SPRxClk, SPTxSync, and SPRxSync must be present for the
loopback mode to function properly for a given port.
Mindspeed Technologies
Alignment
Cell
ATM Cell Transmitter
ATM Cell Receiver
VPI/VCI Screening
Cell Validation
™
4-cell
FIFO
4-cell
FIFO
Interface
Interface
Transmit
UTOPIA
UTOPIA
Receive
Level 2
Level 2
IMA
IMA
CX28224/5/9 Data Sheet
UTOPIA
Level 2
Interface
atmUTxClk
atmUTxClAv
atmUTxEnb*
atmUTxSOC
atmUTxData[15:0]
atmUTxPrty
atmUTxAddr[4:0]
atmURxClk
atmURxClAv
atmURxEnb*
atmURxSOC
atmURxData[15:0]
atmURxPrty
atmURxAddr[4:0]
28229-DSH-001-D
500027_058