cx28224 Mindspeed Technologies, cx28224 Datasheet - Page 145

• Manufacturer Part Number: cx28224
• Description: Cx28224/5/9 Inverse Multiplexing For The Atm Ima Family
• Manufacturer: Mindspeed Technologies

CX28224/5/9 Data Sheet
28229-DSH-001-D
Bit
Bit
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Default
Default
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0x17—TXIDL4 (Transmit Idle Cell Header Control Register 4)
0x18—RXHDR1 (Receive Cell Header Control Register 1)
TxIdl4[7]
TxIdl4[6]
TxIdl4[5]
TxIdl4[4]
TxIdl4[3]
TxIdl4[2]
TxIdl4[1]
TxIdl4[0]
RxHdr1[7]
RxHdr1[6]
RxHdr1[5]
RxHdr1[4]
RxHdr1[3]
RxHdr1[2]
RxHdr1[1]
RxHdr1[0]
The TXIDL4 register contains the fourth byte of the Transmit Idle Cell Header. (See
0x14—TXIDL1.)
The RXHDR1 register contains the first byte of the Receive Cell Header. The header
values direct ATM cells to the UTOPIA port if an incoming ATM cell header matches
the value in the header register. Receive Header Mask Registers further qualify ATM
cell reception. This header consists of 32 bits divided among four registers.
Name
Name
Mindspeed Technologies
These bits hold the Transmit Idle Cell Header values for Octet 4 of the outgoing cell.
These bits hold the Receive Header values for Octet 1 of the incoming cell.
VCI bits
Payload-type bits
Cell Loss Priority bit
Description
Description
™
Registers
7
-
45