cx28224 Mindspeed Technologies, cx28224 Datasheet - Page 249

• Manufacturer Part Number: cx28224
• Description: Cx28224/5/9 Inverse Multiplexing For The Atm Ima Family
• Manufacturer: Mindspeed Technologies

CX28224/5/9 Data Sheet
A.5.3
Table A-1. Basic IMA Protocol (BIP) Definition Functions (1 of 5)
28229-DSH-001-D
BIP.1
BIP.2
BIP.3
BIP.4
BIP.5
BIP.6
BIP.7
BIP.8
BIP.9
BIP.10
BIP.11
BIP.12
BIP.13
BIP.14
BIP.15
BIP.16
BIP.17
Item
Does the implementation support a number N (1 ≤ N ≤ 32) of
transmission links within an IMA group operating at the same
nominal link cell rate (LCR)?
Does the implementation support the IMA interface connected to
another interface over clear channel facilities (implies cells
generated by transmit IMA shall only be terminated at the receive
IMA)?
Does the interface specific TC sublayer of the implementation pass
all cells to the IMA sublayer or provide an indication that a cell was
received (this includes HEC errored cells)?
Does the implementation prohibit cell rate decoupling at the
interface specific TC sublayer?
Does the implementation assign a LID unique within the IMA
group to each Tx IMA link on each physical link?
Does the implementation ensure that the LID does not change
while the link is a member of the IMA group?
Does the implementation distribute ATM cells arriving from the
ATM layer over the N links in a cyclic round-robin fashion, and on a
cell-by-cell basis?
Does the implementation distribute ATM cells over the links using
an ascending order based on the LID assigned to each link within
the IMA group?
Does the implementation support the ICP cell format defined in
Table 2 on page 31 to convey IMA configuration, synchronization,
status, and defect information to the far-end?
Does the implementation perform cell rate decoupling by inserting
IMA Filler cells in place of ATM cells when there is no cell available
at the ATM layer?
Does the implementation accept, on receive, ATM cells from the N
links according to ascending order based on the LID received in
the ICP cells on the incoming link?
Does the implementation, on receive, compensate for link
differential delays and rebuild the original ATM cell stream?
Does the implementation discard received Filler cells and cells with
bad HEC?
Does the implementation process and discard incoming ICP cells?
Does the implementation aggregate, on receive, the ATM cell
stream to the ATM layer?
Does the implementation preserve the order of incoming cells?
Does the implementation use the ICP cell to maintain IMA protocol
synchronization?
IMA Protocol Functions
Protocol feature
Mindspeed Technologies
Cond. for
Status
™
Status
Pred.
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
(R-1)
(R-2)
(R-3)
(R-4)
(R-5)
(R-6)
(R-7)
(R-8)
(R-9)
(R-10)
(R-11)
(R-11)
(R-11)
(R-11)
(R-11)
(R-11)
(R-12)
IMA Version 1.1 PICS Proforma
Ref.
Yes X No__
1 ≤ N ≤ 8
Yes X No__
Yes X No__
Yes X No__
Yes X No__
Yes X No__
Yes X No__
Yes X No__
Yes X No__
Yes X No__
Yes X No__
Yes X No__
Yes X No__
Yes X No__
Yes X No__
Yes X No__
Yes X No__
Support
A
-
3