cx28224 Mindspeed Technologies, cx28224 Datasheet - Page 165

• Manufacturer Part Number: cx28224
• Description: Cx28224/5/9 Inverse Multiplexing For The Atm Ima Family
• Manufacturer: Mindspeed Technologies

CX28224/5/9 Data Sheet
28229-DSH-001-D
5–0
7–6
2–0
7–2
1–0
Bit
Bit
Bit
7
6
5
4
3
Default
000000
Default
Default
000000
000
11
00
0
1
0
0
0
0x201—PHYINTFC (PHY-side Interface Control Register)
0x202—ATMINTFC (ATM-side Interface Control Register)
0x203—OUTSTAT (Output Status Control Register)
ATMmux[1:0]
DisTCUtopia
StatOut[1:0]
BusWidth
Name
Name
Name
—
—
—
—
—
—
Mindspeed Technologies
Reserved, set to 0.
When set to 1, the internal IMA/TC UTOPIA interface is disabled.
Reserved, set to zero.
Controls the ATM-side UTOPIA interface mux.
When set to 0, the 16-bit UTOPIA bus is enabled. When set to 1, the 8-bit UTOPIA
bus is enabled. When the ATM UTOPIA interface to IMA32 block is enabled
(ATMmux[1:0] = "01"), this bit controls the bus width of the IMA32 core ATM-side
UTOPIA interface. In this case, the TC ATM-side UTOPIA interface is always 8-bit.
When the ATM UTOPIA interface to TC block is enabled, (ATMmux[1:0] = "10"),
this bit controls the bus width of the TC ATM-side UTOPIA interface.
Reserved, set to zero.
Reserved, set to zero.
Reserved, set to zero.
Reserved, set to zero.
The value written into these bits will be asserted on the StatOut[1:0] output pins.
00 – External interface is placed in Tristate mode.
01 – Utopia level 2 interface to IMA32 block is enabled.
10 – Utopia level 2 interface to TC block is enabled.
11 – External interface is placed in Tristate mode.
™
Description
Description
Description
Registers
7
-
65