cx28224 Mindspeed Technologies, cx28224 Datasheet - Page 95

• Manufacturer Part Number: cx28224
• Description: Cx28224/5/9 Inverse Multiplexing For The Atm Ima Family
• Manufacturer: Mindspeed Technologies

6.1
6.1.1
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Micro Interface
Resets
General Issues
The microprocessor interface transfers control and status information in 8-bit data
transfers between the external microprocessor and CX2822x by means of write and/or
read access to internal registers. This interface allows the microprocessor to configure
the CX2822x by writing various control registers. These control registers can also be
read for configuration confirmation. This interface also provides the ability to read the
device’s current condition via its status registers and counters. Summary status is
available for rapid interrupt identification.
The microprocessor interface can operate in either an asynchronous mode or a
synchronous mode. The MSyncMode pin (N5) determines which mode is active.
In the synchronous mode, the timing of these signals is synchronized to MicroClk,
which is intended to be directly driven by the external microprocessor. This interface
is compatible with the RS8236 and CN8237 SAR devices, providing no-wait-state
operation.
There are four software controlled reset functions, two at the device level and two at
the port level. The two levels allow a user to reset either the entire CX2822x with one
command or only a port within the device. The two logic resets allow the user to keep
the device or port in a reset state while the control registers are being programmed.
When the reset bit is deasserted, all changes to the registers take place simultaneously.
At the device level, the software-controlled DevMstRst, bit 7, in the MODE register
(0x0200), restarts all device functions and sets the control and status registers,
including IMA, to their default values except this bit (DevMstRst). The DevLgcRst,
bit 6, in the MODE register (0x0200) restarts all device functions in the TC block but
leaves all control registers unaffected.
At the port level, the PrtMstRst, bit 7, in the PMODE register (0x04), restarts all port
functions and sets the registers for the associated port to their default values except
this bit (PrtMstRst). The PrtLgcRst, bit 6, in the PMODE register (0x04) restarts all
functions but leaves the port control registers unaffected.
NOTE:
The MicroClk is required for both modes. In asynchronous mode, a
MicroClk frequency of up to 50MHz, must be present but can be
asynchronous to the other microprocessor signals. In synchronous mode,
MicroClk is limited to 25MHz.
Mindspeed Technologies
™
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