cx28224 Mindspeed Technologies, cx28224 Datasheet - Page 142

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cx28224

Manufacturer Part Number
cx28224
Description
Cx28224/5/9 Inverse Multiplexing For The Atm Ima Family
Manufacturer
Mindspeed Technologies
Datasheet
Registers
7-42
Bit
Bit
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Default
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0x11—TXHDR2 (Transmit Cell Header Control Register 2)
0x12—TXHDR3 (Transmit Cell Header Control Register 3)
TxHdr2[7]
TxHdr2[6]
TxHdr2[5]
TxHdr2[4]
TxHdr2[3]
TxHdr2[2]
TxHdr2[1]
TxHdr2[0]
TxHdr3[7]
TxHdr3[6]
TxHdr3[5]
TxHdr3[4]
TxHdr3[3]
TxHdr3[2]
TxHdr3[1]
TxHdr3[0]
The TXHDR2 register contains the second byte of the Transmit Cell Header. (See
0x10—TXHDR1.)
The TXHDR3 register contains the third byte of the Transmit Cell Header. (See
0x10—TXHDR1.)
Name
Name
Mindspeed Technologies
These bits hold the Transmit Header values for Octet 2 of the outgoing cell. Insertion
of the bits is controlled by the HDRFIELD register (0x09).
These bits hold the Transmit Header values for Octet 3 of the outgoing cell. Insertion
of the bits is controlled by the HDRFIELD register (0x09).
VPI bits
VCI bits
VCI bits
Description
Description
CX28224/5/9 Data Sheet
28229-DSH-001-D

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