cx28224 Mindspeed Technologies, cx28224 Datasheet - Page 63

• Manufacturer Part Number: cx28224
• Description: Cx28224/5/9 Inverse Multiplexing For The Atm Ima Family
• Manufacturer: Mindspeed Technologies

CX28224/5/9 Data Sheet
2.5
Figure 2-8. Source Loopback Diagram (This only shows the TC Block. IMA Block in pass-through mode.)
28229-DSH-001-D
SPTxSync
SPTxData
SPTxClk
Interface
Framer
(Line)
This segment is replicated for Ports 0 - 7
Loopback
Control
Source Loopback (UTOPIA-to-Serial Configuration
Only)
Source loopback checks that the host (the ATM layer) is communicating with the
PHY. It is enabled and disabled in bit 5 of the PMODE register (0x04). When source
loopback is enabled for a given port, all data transmitted by the CX2822x on that port
is also looped back through the Receive Line Interface. Data from the framer interface
is ignored.
NOTE:
TC Transmit Port
TC Receive Port
During Source loopback, the port is automatically placed in General
Purpose mode and MicroClk used as the clock to loop back cells. As a
result of the automatic mode switch and clock used, the data on the Tx
serial lines will be corrupted.
Mindspeed Technologies
Alignment
Cell
ATM Cell Transmitter
ATM Cell Receiver
VPI/VCI Screening
Cell Validation
™
4-cell
FIFO
4-cell
FIFO
Interface
Transmit
Interface
UTOPIA
Receive
UTOPIA
Level 2
Level 2
Host
Host
CX2822x Hardware Description
UTOPIA
Level 2
Interface
atmUTxClk
atmUTxClAv
atmUTxEnb*
atmUTxSOC
atmUTxData[15:0]
atmUTxPrty
atmUTxAddr[4:0]
atmURxClk
atmURxClAv
atmURxEnb*
atmURxSOC
atmURxData[15:0]
atmURxPrty
atmURxAddr[4:0]
500027_017
2
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