cx28224 Mindspeed Technologies, cx28224 Datasheet - Page 30

• Manufacturer Part Number: cx28224
• Description: Cx28224/5/9 Inverse Multiplexing For The Atm Ima Family
• Manufacturer: Mindspeed Technologies

CX2822x Hardware Description
Figure 2-1. CX28229 Logic Diagram (UTOPIA-to-UTOPIA)
2-2
Address Strobe, Write Control
PHY Transmit Address Bus
ATM Transmit Address Bus
PHY Receive Address Bus
ATM Receive Address Bus
Write/Read, Read Control
Sync/Async Mode Select
External Memory Select I
Microprocessor Clock
PHY Transmit Enable
PHY Receive Enable
ATM Transmit Enable
ATM Receive Enable
IMA Reference Clock
Phy Interface Select I
PHY Transmit Clock
PHY Receive Clock
ATM Transmit Clock
ATM Receive Clock
Memory Data Bus
IMA System Clock
Test Mode Select
Test Data Input
8kHzIn Clock
Address Bus
Test Enable
Chip Select
Test Reset
Test Clock
Test Mode
Reset
I/O
I
I
I
O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
phyURxClk
phyURxEnb[1:0]*
phyURxAddr[4:0]
PhyIntFcSel
atmURxEnb*
atmURxClk
atmURxAddr[4:0]
IMA_SysClk
MemData[15:0]
ExtMemSel
phyUTxClk
phyUTxEnb[1:0]*
phyUTxAddr[4:0]
MSyncMode
MicroClk
MCS*
MAS*, MWr*
MicroAddr[10:0]
TRST*
TCK
TMS
TDI
TestEnable
TestMode
atmUTxClk
atmUTxEnb*
atmUTxAddr[4:0]
IMA_RefClk
MW/R, MRd*
Reset*
8kHzIn
Mindspeed Technologies
PHY UTOPIA Transmit
PHY UTOPIA Receive
ATM UTOPIA Transmit
ATM UTOPIA Receive
(1)
External Memory
One Second
Microprocessor
IMA Clocks
Interface
Interface
Interface
Interface
Interface
Interface
Interface
Reset
Interface
JTAG
atmURxData[15:0]
atmUTxData[15:0]
phyURxData[7:0]
phyURxClAv[1:0]
phyUTxData[7:0]
phyUTxClAv[1:0]
MemCtrl_ADSC
MemAddr[19:0]
MicroData[7:0]
MemCtrl_WE*
MemCtrl_OE*
MemCtrl_CLK
MemCtrl_CE*
atmURxSOC
phyURxSOC
atmUTxSOC
atmURxClAv
phyUTxSOC
atmUTxClAv
StatOut[1:0]
atmURxPrty
atmUTxPrty
TxTRL[1:0]
OneSecIO
MicroInt*
MRdy
TDO
™
I/O
I/O
O Status Output
O
O
O
O
O
O
O
O
O
O ATM Receive Data Bus
O Transmit Reference Clock
O
O
O
O Write Enable
O
O Address Enable
I
I
I
I PHY Receive Data Bus
I
I
I
Ready
Microprocessor Data Bus
One Second Input/Output
PHY Transmit Cell Available
PHY Transmit Start Of Cell
PHY Transmit Data Bus
PHY Receive Cell Available
PHY Receive Start of Cell
Summary Interrupt
Test Data Output
ATM Transmit Cell Available
ATM Transmit Start Of Cell
ATM Transmit Parity
ATM Transmit Data Bus
ATM Receive Cell Available
ATM Receive Start of Cell
ATM Receive Parity
Memory Address Bus
Chip Enable
Output Enable
SRAM Clock
CX28224/5/9 Data Sheet
28229-DSH-001-D
(1) Tied Low
500027_003a