cx28224 Mindspeed Technologies, cx28224 Datasheet - Page 202

• Manufacturer Part Number: cx28224
• Description: Cx28224/5/9 Inverse Multiplexing For The Atm Ima Family
• Manufacturer: Mindspeed Technologies

0x4D1 0x4D5 0x4D9 0x4DD 0x5D1 0x5D5 0x5D9 0x5DD 0x6D1 0x6D5 0x6D9 0x6DD 0x7D1 0x7D5 0x7D9 0x7DD
n=1
2–0
CX28224
Bit
Registers
7-102
7
6
5
4
3
n=2
CX28225
Default
0x0
—
—
0
0
0
n=3
Group Enable
SW Timeout Expired
Resync Group
Drain Buffer
Group Size
IMA_RX_GRPn_CTL (Receive Group Control Register)
n=4
Name
—
This register, in conjunction with the IMA_RX_GRPn_CFG and
IMA_RX_GRPn_FIRST_PHY_ADDR registers, controls the operation of the
Receive IMA group.
Group 1–16 Address
n=5
n=6
1 = Group is established and a round-robin is created
0 = Group is not established
1 = certain LSM transitions (Usable → Active) are allowed
0 = certain LSM transitions (Usable → Active) are blocked
1 = Enables the link differential delay synchronization process
0 = disables the link differential delay synchronization process
This bit is used by the software driver to reset the differential delay in T1/E1 mode:
Reserved. Set to 0.
Sets the number of configured links within group.
Range: 0x0–0x7 (1–8 links in group)
Mindspeed Technologies
1 = Allows the differential delay buffer to drain excess cell buffering.
0 = Normal delay buffering.
n=7
n=8
CX28229
Not Applicable
n=9
n=10
Not Applicable
Description
™
n=11
n=12
n=13
CX28224/5/9 Data Sheet
n=14
28229-DSH-001-D
n=15
n=16