cx28224 Mindspeed Technologies, cx28224 Datasheet - Page 7

• Manufacturer Part Number: cx28224
• Description: Cx28224/5/9 Inverse Multiplexing For The Atm Ima Family
• Manufacturer: Mindspeed Technologies

CX28224/5/9 Data Sheet
28229-DSH-001-D
0x14—TXIDL1 (Transmit Idle Cell Header Control Register 1) . . . . . . . . . . . . . . . . . . . . . . . . . 7-43
0x15—TXIDL2 (Transmit Idle Cell Header Control Register 2) . . . . . . . . . . . . . . . . . . . . . . . . . 7-44
0x16—TXIDL3 (Transmit Idle Cell Header Control Register 3) . . . . . . . . . . . . . . . . . . . . . . . . . 7-44
0x17—TXIDL4 (Transmit Idle Cell Header Control Register 4) . . . . . . . . . . . . . . . . . . . . . . . . . 7-45
0x18—RXHDR1 (Receive Cell Header Control Register 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-45
0x19—RXHDR2 (Receive Cell Header Control Register 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-46
0x1A—RXHDR3 (Receive Cell Header Control Register 3). . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-46
0x1B—RXHDR4 (Receive Cell Header Control Register 4). . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-47
0x1C—RXMSK1 (Receive Cell Mask Control Register 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-47
0x1D—RXMSK2 (Receive Cell Mask Control Register 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-48
0x1E—RXMSK3 (Receive Cell Mask Control Register 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-48
0x1F—RXMSK4 (Receive Cell Mask Control Register 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-49
0x20—RXIDL1 (Receive Idle Cell Header Control Register 1) . . . . . . . . . . . . . . . . . . . . . . . . . 7-49
0x21—RXIDL2 (Receive Idle Cell Header Control Register 2) . . . . . . . . . . . . . . . . . . . . . . . . . 7-50
0x22—RXIDL3 (Receive Idle Cell Header Control Register 3) . . . . . . . . . . . . . . . . . . . . . . . . . 7-50
0x23—RXIDL4 (Receive Idle Cell Header Control Register 4) . . . . . . . . . . . . . . . . . . . . . . . . . 7-51
0x24—IDLMSK1 (Receive Idle Cell Mask Control Register 1) . . . . . . . . . . . . . . . . . . . . . . . . . 7-51
0x25—IDLMSK2 (Receive Idle Cell Mask Control Register 2) . . . . . . . . . . . . . . . . . . . . . . . . . 7-52
0x26—IDLMSK3 (Receive Idle Cell Mask Control Register 3) . . . . . . . . . . . . . . . . . . . . . . . . . 7-52
0x27—IDLMSK4 (Receive Idle Cell Mask Control Register 4) . . . . . . . . . . . . . . . . . . . . . . . . . 7-53
0x28—ENCELLT (Transmit Cell Interrupt Control Register) . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-53
0x29—ENCELLR (Receive Cell Interrupt Control Register) . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-54
0x2C—TXCELLINT (Transmit Cell Interrupt Indication Status Register). . . . . . . . . . . . . . . . . . 7-54
0x2D—RXCELLINT (Receive Cell Interrupt Indication Status Register) . . . . . . . . . . . . . . . . . . 7-55
0x2E—TXCELL (Transmit Cell Status Register) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-56
0x2F—RXCELL (Receive Cell Status Register) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-56
0x30—IDLCNTL (Idle Cell Receive Counter [Low Byte]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-57
0x31—IDLCNTM (Idle Cell Receive Counter [Mid Byte]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-57
0x32—IDLCNTH (Idle Cell Receive Counter [High Byte]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-58
0x33—LOCDCNT (LOCD Event Counter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-58
0x34—TXCNTL (Transmitted Cell Counter [Low Byte]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-59
0x35—TXCNTM (Transmitted Cell Counter [Mid Byte]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-59
0x36—TXCNTH (Transmitted Cell Counter [High Byte]). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-60
0x37—CORRCNT (Corrected HEC Error Counter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-60
0x38—RXCNTL (Received Cell Counter [Low Byte]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-61
0x39—RXCNTM (Received Cell Counter [Mid Byte]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-61
0x3A—RXCNTH (Received Cell Counter [High Byte]). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-62
0x3B—UNCCNT (Uncorrected HEC Error Counter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-62
0x3C—NONCNTL (Non-matching Cell Counter [Low Byte]). . . . . . . . . . . . . . . . . . . . . . . . . . . 7-63
0x3D—NONCNTH (Non-matching Cell Counter [High Byte]) . . . . . . . . . . . . . . . . . . . . . . . . . . 7-63
0x200—MODE (Device Mode Control Register). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-64
0x201—PHYINTFC (PHY-side Interface Control Register) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-65
0x202—ATMINTFC (ATM-side Interface Control Register). . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-65
0x203—OUTSTAT (Output Status Control Register). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-65
0x204—SUMPORT (Summary Port Interrupt Status Register) . . . . . . . . . . . . . . . . . . . . . . . . 7-66
0x205—ENSUMPORT (Summary Port Interrupt Control Register) . . . . . . . . . . . . . . . . . . . . . 7-66
0x208—PART/VER (Part Number/Version Register) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-67
Mindspeed Technologies
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