cx28224 Mindspeed Technologies, cx28224 Datasheet - Page 58

• Manufacturer Part Number: cx28224
• Description: Cx28224/5/9 Inverse Multiplexing For The Atm Ima Family
• Manufacturer: Mindspeed Technologies

CX2822x Hardware Description
Table 2-5. CX28229 Pin Descriptions (9 of 12)
2-30
atmUTxClAv
atmUTxSOC
atmUTxEnb*
atmUTxClk
atmURxSOC
atmURxClk
atmURxClAv
atmURxEnb*
Pin Label
ATM UTOPIA
Transmit Cell
Available
ATM UTOPIA
Transmit Start of Cell
ATM UTOPIA
Transmit Enable
ATM UTOPIA
Transmit Clock
ATM UTOPIA Receive
Start of Cell
ATM UTOPIA Receive
Clock
ATM UTOPIA Receive
Cell Available
ATM UTOPIA Receive
Enable
Signal Name
Mindspeed Technologies
D11
No.
C12
B12
A12
D8
C9
A9
B9
I/O
O
O
O
I
I
I
I
I
Cell Available signal for Transmit ATM cells (active high).
Start of Cell synchronization signal for transmit ATM cells
(active high). Indicates that the first byte/word of the 53
byte cell is being placed on the atmUTxData bus.
Data transfer enable for transmit ATM cells (active low).
Indicates that the first byte/word of the 53 byte cell is being
placed on the atmUTxData bus.
Clock signal used for transfer of transmit ATM cells from
the ATM Layer. The maximum clock rate is 33 MHz.
Start of Cell synchronization signal for receive ATM cells
(active high). Indicates that the first byte/word of the 53
byte cell is being placed on the atmURxData bus.
Clock signal used for transfer of receive ATM cells from the
ATM Layer. The maximum clock rate is 33 MHz.
Cell Available signal for receive ATM cells (active high). As
a software option in the IMA16 application, the pin
atmURxAdr[4] will function as a cell available status signal
(atmURxClAv[1]) for ATM Utopia addresses 8–15 only. In
this mode, atmURxClAv[1] will threestate for addresses 0–
7.
Data transfer and output enable for Receive ATM cells
(active low).
™
Description
CX28224/5/9 Data Sheet
28229-DSH-001-D