cx28224 Mindspeed Technologies, cx28224 Datasheet - Page 59

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cx28224

Manufacturer Part Number
cx28224
Description
Cx28224/5/9 Inverse Multiplexing For The Atm Ima Family
Manufacturer
Mindspeed Technologies
Datasheet
CX28224/5/9 Data Sheet
Table 2-5. CX28229 Pin Descriptions (10 of 12)
28229-DSH-001-D
atmURxData[0]
atmURxData[1]
atmURxData[2]
atmURxData[3]
atmURxData[4]
atmURxData[5]
atmURxData[6]
atmURxData[7]
atmURxData[8]
atmURxData[9]
atmURxData[10]
atmURxData[11]
atmURxData[12]
atmURxData[13]
atmURxData[14]
atmURxData[15]
atmURxPrty
atmURxAddr[0]
atmURxAddr[1]
atmURxAddr[2]
atmURxAddr[3]
atmURxAddr[4]
Pin Label
ATM UTOPIA Receive
Data
ATM UTOPIA Receive
Parity
ATM UTOPIA Receive
Address
Signal Name
Mindspeed Technologies
D10
No.
C11
B11
C10
A11
B10
A10
D5
D9
D4
D3
C8
A8
B8
C7
C5
A5
B5
C4
A4
B4
C3
I/O
O
O
I
Receive direction ATM side cell data.
Parity status signal. In 8 bit Utopia mode, a parity
calculation is performed over atmURxData[7:0] for each
clock cycle of atmURxClk. Odd parity is used. In 16 bit
Utopia mode, this signal is the parity of atmURxData[15:0].
This signal is optional.
Receive ATM Cell Bus address. This address determines
the source channel of the Receive ATM cells output from
the IMA subsystem and also selects the channel sourcing
the atmURxClAv signal. All 5 bits are not required in every
application.
Description
CX2822x Hardware Description
2
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31

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