cx28224 Mindspeed Technologies, cx28224 Datasheet - Page 200

• Manufacturer Part Number: cx28224
• Description: Cx28224/5/9 Inverse Multiplexing For The Atm Ima Family
• Manufacturer: Mindspeed Technologies

Registers
Group 1–16 Address
Group 1–16 Address
7-100
0x450 0x452 0x454 0x456 0x550 0x552 0x554 0x556 0x650 0x652 0x654 0x656 0x750 0x752 0x754 0x756
0x451 0x453 0x455 0x457 0x551 0x553 0x555 0x557 0x651 0x653 0x655 0x657 0x751 0x753 0x755 0x757
n=1
n=1
7-0
7-0
CX28224
Bit
CX28224
Bit
n=2
n=2
CX28225
CX28225
Default
Default
0
0
n=3
n=3
IMA_RX_GRPn_CELL_COUNT_LSB (Receive Cell Count LSBs)
IMA_RX_GRPn_CELL_COUNT_MSB (Receive Cell Count MSBs)
Receive Cell Count LSBs
Receive Cell Count MSBs
n=4
n=4
This register contains the least significant bits of a 16 bit count of the number of ATM
layer cells received over the Receive links within the group. The register is read only.
Status clears upon read.
This register contains the most significant bits of a 16 bit count of the number of ATM
layer cells received over the Receive links within the group. The register is read only.
Status clears upon read.
Name
Name
n=5
n=5
n=6
n=6
Mindspeed Technologies
n=7
n=7
Receive Group Cell Count: This field contains the least significant bits of a 16 bit
count of the number of ATM layer cells received over the Receive links within
the group. A write operation with data = 0x01 to the first address (0x450 for
Group #1, 0x452 for Group #2, etc.) transfers the state of all 16 bits of the
counter to registers that are accessible to the microprocessor bus and clears
the counter. A read operation should then be performed to read the previous
state of the counter. The first address should be read first. The second address
(0x451 for Group #1, 0x453 for Group #2, etc.) is read next. A write operation
with data = 0x00 to the first address of each group returns back to the raw
counters.
Receive Group Cell Count: This field contains the most significant bits of a 16
bit count of the number of ATM layer cells received over the Receive links
within the group. A write operation with data = 0x01 to the first address (0x450
for Group #1, 0x452 for Group #2, etc.) transfers the state of all 16 bits of the
counter to registers that are accessible to the microprocessor bus and clears
the counter. A read operation should then be performed to read the previous
state of the counter. The first address should be read first. The second address
(0x451 for Group #1, 0x453 for Group #2, etc.) is read next. A write operation
with data = 0x00 to the first address of each group returns back to the raw
counters.
n=8
n=8
CX28229
CX28229
Not Applicable
Not Applicable
n=9
n=9
Not Applicable
Not Applicable
n=10
n=10
™
n=11
n=11
Description
Description
n=12
n=12
n=13
n=13
n=14
n=14
CX28224/5/9 Data Sheet
28229-DSH-001-D
n=15
n=15
n=16
n=16